On compaction utilizing inter and intra-correlation of unknown states

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 1, 2010, Pages 117-126

  Czysz, Dariusz ^a   Mrugalski, Grzegorz ^b   Mukherjee, Nilanjan ^b   Rajski, Janusz ^b   Tyszer, Jerzy ^a  

^a POZNAN UNIVERSITY OF TECHNOLOGY   (Poland)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

Output compaction; Scan chain selection; Test data compression; Unknown states; X masking

Indexed keywords

COMPACTION RATIO; CYCLE MODE; HIGH DENSITY; NEW APPROACHES; RANDOMLY DISTRIBUTED; SCAN CELLS; SCAN CHAIN; SELECTION MECHANISM; SEMICONDUCTOR TESTS; SIMILAR PATTERN; TEST DATA; TEST DATA COMPRESSION; TEST QUALITY; TEST RESPONSE; TEST RESULTS; TEST-RESPONSE COMPACTION; UNKNOWN STATE; X-MASKING;

COMPACTION; TEST FACILITIES; TESTING;

DATA COMPRESSION;

EID: 73249140974     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2035550     Document Type: Article

References (35)

1. C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, B. Koenemann, and A. Ferko, "OPMISR: The foundation for compressed ATPG vectors," in Proc. Int. Test Conf., 2001, pp. 748-757.
2. M. C.-T. Chao, S. Wang, S. T. Chakradhar, and K.-T. Cheng, "Response shaper: A novel technique to enhance unknown tolerance for output response compaction," in Proc. Int. Conf. Comput.-Aided Design, 2005, pp. 80-87.
3. V. Chickermane, B. Foutz, and B. Keller, "Channel masking synthesis for efficient on-chip test compression," in Proc. Int. Test Conf., 2004, pp. 452-461.
4. T. Clouqueur, H. Fujiwara, K. Zarrineh, and K. Saluja, "Design and analysis of multiple-weight linear compactors of responses containing unknown values," in Proc. Int. Test Conf., 2005, pp. 1099-1108.
5. D. Czysz, G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer, "Highly X-tolerant selective compaction of test responses," in Proc. VLSI Test Symp., 2009, pp. 245-250.
6. R. Garg, R. Putman, and N. A. Touba, "Increasing output compaction in presence of unknowns using an X-canceling MISR with deterministic observation," in Proc. VLSI Test Symp., 2008, pp. 35-42.
7. A. Leininger, M. Richter, M. Goessel, M. Braun, and M. Fischer, "Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques," in Proc. Int. Test Conf., 2007, paper 6.3.
8. S. Mitra and K. S. Kim, "X-Compact: An efficient response compaction technique," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.23, no.3, pp. 421-432, Mar. 2004.
9. S. Mitra, S. S. Lumetta, and M. Mitzenmacher, "X-tolerant signature analysis," in Proc. Int. Test Conf., 2004, pp. 432-441.
10. G. Mrugalski, J. Rajski, and J. Tyszer, "Test response compactor with programmable selector," in Proc. Design Automat. Conf., 2006, pp. 1089-1094.
11. B. Nadeau-Dostie, "Method of masking corrupt bits during signature analysis and circuit for use therewith," U.S. Patent 6 745 359, Jun. 1, 2004.
12. M. Naruse, I. Pomeranz, S. M. Reddy, and S. Kundu, "On-chip compression of output responses with unknown values using LFSR reseeding," in Proc. Int. Test Conf., 2003, pp. 1060-1068.
13. J. H. Patel, S. S. Lumetta, and S. M. Reddy, "Application of Saluja- Karpovsky compactors to test responses with many unknowns," in Proc. VLSI Test Symp., 2003, pp. 107-112.
14. I. Pomeranz, S. Kundu, and S. M. Reddy, "On output response compression in the presence of unknown output values," in Proc. Design Automat. Conf., 2002, pp. 255-258.
15. T. Rabenalt, M. Goessel, and A. Leininger, "Masking of X-values by use of a hierarchically configurable register," in Proc. Eur. Test Symp., 2009, pp. 149-154.
16. W. Rajski and J. Rajski, "Modular compactor of test responses," in Proc. VLSI Test Symp., 2006, pp. 242-251.
17. J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide, and J. Qian, "Embedded deterministic test for low cost manufacturing test," in Proc. Int. Test Conf., 2002, pp. 301-310. (Pubitemid 35411432)
18. J. Rajski, J. Tyszer, G. Mrugalski, W.-T. Cheng, and M. Kassab, "Multistage test response compactors," U.S. Patent Application 20070234157, Oct. 4, 2007.
19. J. Rajski, J. Tyszer, G. Mrugalski, N. Mukherjee, W.-T. Cheng, and M. Kassab, "X-Press compactor for 1000x reduction of test data," in Proc. Int. Test Conf., 2006, pp. 1-10.
20. J. Rajski, J. Tyszer, G. Mrugalski, N. Mukherjee, W.-T. Cheng, and M. Kassab, "X-Press: Two-stage X-tolerant compactor with programmable selector," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.27, no.1, pp. 147-159, Jan. 2008.
21. J. Rajski, J. Tyszer, C. Wang, and S. Reddy, "Convolutional compaction of test responses," in Proc. Int. Test Conf., 2003, pp. 745-754.
22. M. Sharma and W.-T. Cheng, "X-Filter: Filtering unknowns from compacted test responses," in Proc. Int. Test Conf., 2005, pp. 1090- 1098.
23. O. Sinanoglu and S. Almukhaizim, "X-align: Improving the scan cell observability of response compactors," IEEE Trans. Very-Large-Scale Integration Syst., vol.17, no.10, pp. 1392-1404, Oct. 2009.
24. H. Tang, C. Wang, J. Rajski, S. M. Reddy, J. Tyszer, and I. Pomeranz, "On efficient X-handling using a selective compaction scheme to achieve high-test response compaction ratios," in Proc. VLSI Design, 2005, pp.59-64.
25. Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker, "X-masking during logic BIST and its impact on defect coverage," in Proc. Int. Test Conf., 2003, pp. 442-451.
26. Y. Tang, H.-J. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schloffel, F. Hapke, and M. Wittke, "X-masking during logic BIST and its impact on defect coverage," IEEE Trans. Very-Large-Scale Integration Syst., vol.14, no.2, pp. 193-202, Feb. 2006.
27. N. A. Touba, "X-canceling MISR: An X-tolerant methodology for compacting output responses with unknowns using a MISR," in Proc. Int. Test Conf., 2007, paper 6.2.
28. E. H. Volkerink and S. Mitra, "Response compaction with any number of unknowns using a new LFSR architecture," in Proc. Design Automat. Conf., 2005, pp. 117-122.
29. C. Wang, S. Reddy, I. Pomeranz, J. Rajski, and J. Tyszer, "On compacting test responses data containing unknown values," in Proc. Int. Conf. Comput.-Aided Design, 2003, pp. 855-862.
30. S. Wang, K. J. Balakrishnan, and W. Wei, "X-Block: An efficient LFSR reseeding-based method to block unknowns for temporal compactors," IEEE Trans. Comput., vol.57, no.7, pp. 978-989, Jul. 2008.
31. S. Wang, W. Wei, and S. T. Chakradhar, "Unknown blocking scheme for low control data volume and high observability," in Proc. Design Automation and Test in Europe, 2007, pp. 1-6.
32. S. Wang and W. Wei, "An efficient unknown blocking scheme for low control data volume and high observability," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.27, no.11, pp. 2039-2052, Nov. 2008.
33. P. Wohl, J. A. Waicukauski, and F. Neuveux, "Increasing scan compression by using X-chains," in Proc. Int. Test Conf., 2008, paper 35.1.
34. P. Wohl, J. A. Waicukauski, S. Patel, and A. Amin, "X-tolerant compression and application of scan-ATPG patterns in a BIST architecture," in Proc. Int. Test Conf., 2003, pp. 727-736.
35. P. Wohl, J. Waicukauski, and S. Ramnath, "Fully X-tolerant combinational scan compression," in Proc. Int. Test Conf., 2007, paper 6.1.