Test response compactor with programmable selector

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 1089-1094

  Mrugalski, Grzegorz ^a   Rajski, Janusz ^a   Tyszer, Jerzy ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b POZNAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Compression; Scan chain selection; Unknown states; VLSI test

Indexed keywords

CONTROL SYSTEM ANALYSIS; GATES (TRANSISTOR); VLSI CIRCUITS;

PROGRAMMABLE SELECTORS; SCAN CHAIN SELECTION; TEST RESPONSE COMPACTORS; VLSI TEST;

LOGIC CIRCUITS;

EID: 34547154354     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147184     Document Type: Conference Paper

References (21)

1. Bayraktaroglu, I., and Orailoglu, A. Test volume and application time reduction through scan chain concealment. Proc. DAC, pp. 151-155, 2001.
2. Barnhart, C., Brunkhorst, V., Distler, F., Famsworth, O., Keller, B., and Koenemann, B. OPMISR: The foundation for compressed ATPG vectors. Proc. ITC, pp. 748-757, 2001.
3. Barnhart, C., Brunkhorst, V., Distler, F., Famsworth, O., Ferko, A., Keller, B., Scott, D., Koenemann, B., and Onodera, T. Extending OPMISR beyond 10x scan test efficiency. IEEE Design and Test, vol. 19, No. 5, pp. 65-73, 2002.
4. Butler, K.M., and Powell, T.J. System and method for structurally testing integrated circuit devices. US Patent 5,694, 402, 1997.
5. Chickermane, V., Foutz, B., and Keller, B. Channel masking synthesis for efficient on-chip test compression. Proc. ITC, pp. 452-461, 2004.
6. Clouqueur, T., Fujiwara, H., Zarrineh, K., and Saluja, K. Design and analysis of multiple-weight linear compactors of responses containing unknown values. Proc. ITC, 2005, paper 42.2.
7. Mitra S., and Kim, K. S. X-Compact: an efficient response compaction technique. IEEE Trans. CAD, vol. 23, pp. 421-432, March 2004.
8. Mitra, S., Lumetta, S.S., and Mitzenmacher, M. X-tolerant signature analysis. Proc. ITC, pp. 432-441, 2004.
9. Naruse, M., Pomeranz, I., Reddy, S.M., and Kundu, S. Onchip compression of output responses with unknown values using LFSR reseeding. Proc. ITC, pp. 1060-1068, 2003.
10. Nadeau-Dostie, B. Method of masking corrupt bits during signature analysis and circuit for use therewith. US Patent 6,745,359, 2004.
11. Patel, J. H., Lumetta, S. S., and Reddy, S. M. Application of Saluja-Karpovsky compactors to test responses with many unknowns. Proc. VTS, pp. 107-112, 2003.
12. Pomeranz, I., Kundu, S., and Reddy, S.M. On output response compression in the presence of unknown output values. Proc. DAC, pp. 255-258, 2002.
13. Rajski, J., Tyszer, J., Kassab, M., Mukherjee, N., Thompson, R., Tsai, H., Hertwig, A., Tamarapalli, N., Mrugalski, G., Eide, G., and Qian, J. Embedded deterministic test for low cost manufacturing test. Proc. ITC, pp. 301-310, 2002.
14. Rajski, J., Tyszer, J., Wang, C., and Reddy, S.M. Convolutional compaction of test responses. Proc. ITC, pp.745-754, 2003.
15. Sharma M., and Cheng, W-T. X-Filter: Filtering unknowns from compacted test responses. Proc. ITC, 2005, paper 42.1.
16. Tang, H., Wang, C., Rajski, J., Reddy, S.M., Tyszer, J., and Pomeranz, I. On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios. Proc. VLSI Design, 2005.
17. Tang, Y., Wunderlich, H-J., Vranken, H., Hapke, F., Wittke, M., Engelke, P., Polian, I., and Becker, B. X-masking during logic BIST and its impact on defect coverage. Proc. ITC, pp. 442-451, 2003.
18. Wang, C., Reddy, S.M., Pomeranz, I., Rajski, J., and Tyszer, J. On compacting test responses data containing unknown values. Proc. ICCAD, pp. 855-862, 2003.
19. Wohl, P., Waicukauski, J.A., Patel, S., and Amin, A. X-tolerant compression and application of scan-ATPG patterns in a BIST architecture. Proc. ITC, pp. 727-736, 2003.
20. Wu, Y. Methods and apparatus for fault diagnosis in self-testable systems. US Patent 5,831,992, 1998.
21. Volkerink E.H., and Mitra, S. Response compaction with any number of unknowns using a new LFSR architecture. Proc. DAC, pp. 117-122, 2005.