Design and analysis of multiple weight linear compactors of responses containing unknown values

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 1099-1108

  Clouqueur, Thomas ^a   Zarrineh, Kamran ^b   Saluja, Kewal K ^c   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b AMD   (United States)

^c UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; EQUIPMENT TESTING; MASKS;

COMPACTION RATIO; HARDWARE OVERHEAD; LINEAR COMPACTORS; LINEAR TEST OUTPUT COMPACTORS; MASKING; SCAN CHAINS; TEST RESPONSE;

AUTOMATIC TESTING;

EID: 33847093724     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584077     Document Type: Conference Paper

References (26)

1. B. Bhattacharya, A. Dmitriev, M. Gossel, and K. Charkrabarty, "Synthesis of single-output space compactors for scan-based sequential circuits," IEEE Trans. on CAD, vol. 21, pp. 1171-1179, October 2002.
2. K. Chakrabarty, "Zero-aliasing space compaction using linear compactors with bounded overhead," IEEE Trans. on CAD, vol. 17, pp. 452-457, May 1998.
3. K. Chakrabarty and J. P. Hayes, "Zero-aliasing space compaction of test responses using multiple parity signatures," IEEE Trans. on VLSI Systems, vol. 6, pp. 309-313, June 1998.
4. K. Chakrabarty, B. T. Murray, and J. P. Hayes, "Optimal zero-aliasing space compaction of test responses," IEEE Trans, on Computers, vol. 47, pp. 1171-1187, November 1998.
5. V. Chickermane, B. Foutz, and B. Keller, "Channel masking synthesis for efficient on-chip test compression," in Proc. ITC, pp. 452-461, 2004.
6. I. Hamzaoglu and J. H. Patel, "Reducing test application time for full scan embedded cores," in Proc. of FTCS, pp. 260-267, 1999.
7. Y. Han, Y. Hu, H. Li, X. Li, and A. Chandra, "Response compaction for test time and test pins reduction based on advanced convolutional codes," in Proc. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 298-305, 2004.
8. Y. Han, Y. Xu, H. Li, X. Li, and A. Chandra, "Test resource partitioning based on efficient response compaction for test time and tester channels reduction," in Proc. ATS, pp. 440-445, 2003.
9. M. Hsiao, "A class of optimal minimum odd-weight-column sec-ded codes," IBM Journal of Research and Development, vol. 14, pp. 395-401, July 1970.
10. A. Ivanov, B. Tsuji, and Y. Zorian, "Programmable bist compactors," IEEE Trans. on Computers, vol. 45, pp. 1393-1404, December 1996.
11. A. Jas, J. Ghosh-Dastidar, and N. Touba, "Scan vector compression/decompression using statistical coding," in Proc. VTS, pp. 114-120, 1999.
12. B. Koenemann, "Lfsr-coded test patterns for scan designs," in Proc. European Test Conference, pp. 237-242, 1991.
13. Y. K. Li and J. P. Robinson, "Space compression methods with output data modification," IEEE Trans. on CAD, vol. 6, pp. 290-294, March 1987.
14. E. McCluskey, D. Burek, B. Koenemann, S. Mitra, J. Patel, J. Rajski, and J. Waicukauski, "Test data compression," Design & Test of Computers, IEEE, vol. 20, pp. 76-87, Mar-Apr 2003.
15. S. Mitra and K. S. Kim, "X-compact an efficient response compaction technique," IEEE Trans. on CAD, vol. 23, pp. 421-432, March 2004.
16. S. Mitra, S. S. Lumetta, and M. Mitzenmacher, "X-tolerant signature analysis," in Proc. ITC, pp. 432-441, 2004.
17. M. Naruse, I. Pomeranz, S. M. Reddy, and S. Kundu, "On-chip compression of output responses with unknown values using lfsr reseeding," in Proc. ITC, pp. 1060-1068, 2003.
18. J. H. Patel, S. S. Lumetta, and S. M. Reddy, "Application of saluja-karpovsky compactors to test responses with many unknowns," in Proc. VTS, pp. 107-112, 2003.
19. I. Pomeranz, S. Kundu, and S. M. Reddy, "On output response compression in the presence of unknown output values," in Proc. DAC, pp. 255-258, 2002.
20. B. Pouya and N. A. Touba, "Synthesis of zero-aliasing elementary-tree space compactors," in Proc. VTS, pp. 70-77, 1998.
21. J. Rajski, J. Tyszer, C. Wang, and S. M. Reddy, "Convolutional compaction of test responses," in Proc. ITC, pp. 745-754, 2003.
22. K. K. Saluja and M. Karpovsky, "Testing computer hardware through data compression in space and time," in Proc. ITC, pp. 83-88, 1983.
23. O. Sinanoglu and A. Orailoglu, "Efficient construction of aliasing-free compaction circuitry," IEEE Micro, vol. 22, pp. 82-92, Sept-Oct 2002.
24. H. Tang, C. Wang, J. Rajski, S. M. Reddy, J. Tyszer, and I. Pomeranz, "On efficient x-handling using a selective compaction scheme to achieve high test response compaction ratios," in Proc. VLSI Design, pp. 59-64, 2005.
25. Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker, "X-masking during logic bist and its impact on defect coverage," in Proc. ITC, pp. 442-451, 2004.
26. C. Wang, S. M. Reddy, I. Pomeranz, J. Rajski, and J. Tyszer, "On compacting test response data containing unknown values," in Proc. ICCAD, pp. 855-862, 2003.