X-tolerant compression and application of scan-ATPG patterns in a BIST architecture

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 727-736

  Wohl, Peter ^a   Waicukauski, John A ^a   Patel, Sanjay ^a   Amin, Minesh B ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; LOGIC CIRCUITS; LOGIC GATES;

AUTOMATIC TEST PATTERN GENERATION (ATPG);

BUILT-IN SELF TEST;

EID: 0142215972     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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