Channel masking synthesis for efficient on-chip test compression

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 452-461

  Chickermane, Vivek ^a   Foutz, Brian ^a   Keller, Brion ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COST EFFECTIVENESS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; RELIABILITY; VLSI CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); CHANNEL MASKING; DENSITY FUNCTIONAL THEORY (DFT); LOGIC TEST COMPRESSION;

BUILT-IN SELF TEST;

EID: 18144423558     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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