X-Align: Improving the scan cell observability of response compactors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 10, 2009, Pages 1392-1404

  Sinanoglu, Ozgur ^a   Almukhaizim, Sobeeh ^a  

^a KUWAIT UNIVERSITY   (Kuwait)

Author keywords

Error masking; Output compaction; Test response compaction; Unknown response bits; X align

Indexed keywords

ERROR MASKING; OUTPUT COMPACTION; TEST RESPONSE COMPACTION; UNKNOWN RESPONSE BITS; X-ALIGN;

ALIGNMENT; CELL MEMBRANES; INTEGER PROGRAMMING; LINEARIZATION; SCANNING; TESTING;

COMPACTION;

EID: 70349739367     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2004589     Document Type: Article

References (21)

1. J. Savir, "Reducing the MISR size," IEEE Trans. Comput., vol.45, no.8, pp. 930-938, Aug. 1996.
2. A. Ivanov, B. Tsuji, and Y. Zorian, "Programmable BIST space compactors," IEEE Trans. Comput., vol.45, no.12, pp. 1393-1404, Dec. 1996.
3. C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, "OPMISR: The foundation for compressed ATPG vectors," in Proc. Int. Test Conf., 2001, pp. 748-757.
4. V. Chickermane, B. Foutz, and B. Keller, "Channel masking synthesis for efficient on-chip test compression," in Proc. Int. Test Conf., 2004, pp. 452-461.
5. B. Pouya and N. Touba, "Synthesis of zero-aliasing space elementary-tree space compactors," in Proc. IEEE VLSI Test Symp., 1998, pp. 70-77.
6. K. Chakrabarty, "Zero-aliasing space compaction using linear compactors with bounded overhead," IEEE Trans. Comput.-Aided Design, vol.17, no.5, pp. 452-457, May 1998.
7. K. Chakrabarty and J. P. Hayes, "Test response compaction using multiplexed parity trees," IEEE Trans. Comput.-Aided Design, vol.15, no.11, pp. 1399-1408, Nov. 1996.
8. O. Sinanoglu and A. Orailoglu, "Compacting test buses for deeply embedded SOC cores," IEEE Design and Test, vol.20, no.4, pp. 22-30, 2004.
9. O. Sinanoglu and A. Orailoglu, "Efficient construction of aliasing-free compaction circuitry," IEEE Micro, vol.22, no.5, pp. 82-92, 2004.
10. O. Sinanoglu and A. Orailoglu, "Parity-based output compaction for core-based SOCs," in Proc. Eur. Test Workshop, 2003, pp. 15-20.
11. P. Wohl, J. A. Waicukauski, and T. W. Williams, "Design of compactors for signature analyzers in built-in self-test," in Proc. Int. Test Conf., 2001, pp. 54-63.
12. S. Mitraand K. S. Kim, "X-Compact: An efficient response compaction technique for test cost reduction," in Proc. Int. Test Conf., 2002, pp. 311-320.
13. I. Pomeranz, S. Kundu, and S. M. Reddy, "Masking of unknown output values during output response compression by using comparison units," IEEE Trans. Comput., vol.53, no.1, pp. 83-89, Jan. 2004.
14. M. C.-T. Chao, S. Wang, S. T. Chakradhar, and K.-T. Cheng, "Response shaper: A novel technique to enhance unknown tolerance for output response compaction," in Proc. Int. Conf. Comput.-Aided Design, 2005, pp. 80-87.
15. J. Rajski and J. Tyszer, "Synthesis of X-tolerant convolutional compactors," in Proc. VLSI Test Symp., 2005, pp. 114-119.
16. M. Arai, S. Fukumoto, and K. Iwasaki, "Analysis of error-masking and X-masking probabilities for convolutional compactors," in Proc. Int. Test Conf., 2005, pp. 24.1.1-24.1.10.
17. T. Clouqueur, K. Zarrineh, K. K. Saluja, and H. Fujiwara, "Design and analysis of multiple weight linear compactors of responses containing unknown values," in Proc. Int. Test Conf., 2005, pp. 24.2.1-24.2.10.
18. W. Rajski and J. Rajski, "Modular compactor of test responses," in Proc. VLSI Test Symp., 2006.
19. M. Amodeo and B. Cory, "Beyond at speed," in Proc. TestMeas. World, 2005, pp. 242-251.
20. N. Ahmed, M. Tehranipoor, and V. Jayaram, "A novel framework for faster-than-at-speed delay test considering IR-drop effects," in Proc. Int. Conf. Comput.-Aided Design, 2006, pp. 198-203.
21. P. Raghavan and C. Thompson, "Randomized rounding: A technique for provably good algorithms and algorithmic proofs," Combinatorica, vol.7, no.4, pp. 365-374, 1987.