Response shaper: A novel technique to enhance unknown tolerance for output response compaction

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 80-87

  Chao, Mango C T ^a   Wang, Seongmoon ^b   Chakradhar, Srimat T ^b   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONVOLUTIONAL COMPACTORS; RESHAPING ALGORITHM; RESPONSE SHAPERS; SPACE COMPACTORS;

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; SIGNAL PROCESSING;

RESPONSE TIME (COMPUTER SYSTEMS);

EID: 33751403124     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560044     Document Type: Conference Paper

References (16)

1. A. Jas, J. Gohosh-Dastidar, and N. A. Touba, Scan Vector Compression/Decompression Using Statistical Coding, IEEE VLSI Test Symposium, pp.114-120, 1999.
2. P. T. Gonciari, B. M. Al-Hashimi, and N. Nicholici, Improving Compression Ratio, Area Overhead, and Test Application Time for System-On-a-Chip Test Data Compression/Decompression, ACM/IEEE Design, Automation and Test in Europe Conference and Exhibition, pp.604-611, 2002.
3. B. Koenemann, LFSR-Coded Test Patterns for Scan Designs, European Test Conference, pp.237-242, 1991.
4. H. G. Liang, S. Hellebrand, and H. J. Wunderlich, Two-Dimentional Test Data Compression for Scan-Based Deterministic BIST, IEEE International Test Conference, pp.894-902, 2001.
5. S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez, and J. Figueras, BIST technique by equally spaced test vector sequences, IEEE VLSI Test Symposium, pp.530-537, 2004.
6. W. Rao, I. Bayraktaroglu, and A. Orailoglu, Test Application Time and Volumn Compression through Seed Overlapping, ACM/IEEE Design Automation Conference, pp.732-737, 2003.
7. C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, OPMISR: The Foundation for Compressed ATPG Vectors, IEEE International Test Conference, pp.748-757, 2001.
8. I. Pomeranz, S. Kundu, and S. M. Reddy, Masking of Unknown Output Values during Output Response Compression by Using Comparison Units, IEEE Transactions on Computers, Vol. 53, No. 1, Jan, pp.83-89, 2004.
9. Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker, X-Masking During Logic BIST and Its Impact on Defect Coverage, IEEE International Test Conference, pp.442-451, 2004.
10. V. Chickermane, B. Foutz, and B. Keller, Channel Masking Synthesis for Efficient On-Chip Test Compression, IEEE International Test Conference, pp.452-460, 2004.
11. P. Wohl, J. A. Waicukauski, S. Patel, and M. B. Amin, X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture, IEEE International Test Conference, pp.727-736, 2003.
12. J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, Selective Linear Compactor of Test Responses with Unknown Values, USA pending patent application, 2002.
13. H. Tang, C. Wang, J. Rajski, S. M. Meddy, J. Tyszer, and I. Pomeranz, On Efficient X-handling Using a Selective Compaction Scheme to Achieve High Test Tesponse Compaction Ratios, IEEE International Conference on VLSI Design, pp.59-64, 2005.
14. S. Mitra, and K. S. Kim, X-Compact: an efficient response compaction technique for test cost reduction, IEEE International Test Conference, pp.311-320, 2002.
15. C. Wang, S. M. Reddy, I. Pomeranz, J. Rajski, and J. Tyszer, On Compacting Test Response Data Containing Unknown Values, ACM/IEEE International Conference on Computer Aided Design, pp.855-862, November 2003.
16. J. Rajski, C. Wang, and S. M. Reddy, Convolutional Compaction Of Test Responses, IEEE International Test Conference, pp. 745-754, 2003.