X-masking during logic BIST and its impact on defect coverage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 2, 2006, Pages 193-202

  Tang, Yuyi ^b   Wunderlich, Hans Joachim ^a,b   Engelke, Piet ^a,c   Polian, Ilia ^a,c   Becker, Bernd ^a,c   Schlöffel, Jürgen ^a,d,e,f   Hapke, Friedrich ^d,f   Wittke, Michael ^d  

^a IEEE

^b UNIVERSITY OF STUTTGART   (Germany)

^c UNIVERSITY OF FREIBURG   (Germany)

^d PHILIPS RESEARCH LABORATORIES   (Germany)

^e ITG Working Group

^f Albert Ludwigs University ^*  (Germany)

Author keywords

Defect coverage; Logic built in seiftest (BIST); Resistive bridging faults (RBFs); X masking

Indexed keywords

DEFECT COVERAGE; RESISTIVE BRIDGING FAULTS (RBFS); X-MASKING;

BUILT-IN SELF TEST; DEFECTS; MATHEMATICAL MODELS; PROBABILITY; SILICON;

VLSI CIRCUITS;

EID: 33645002270     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.863742     Document Type: Article

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