On output response compression in the presence of unknown output values

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 255-258

  Pomeranz, Irith ^a   Kundu, Sandip ^b   Reddy, Sudhakar M ^c  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

OUTPUT RESPONSE ANALYZERS (ORA);

BUILT-IN SELF TEST; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; ELECTRIC NETWORK ANALYZERS;

SEQUENTIAL CIRCUITS;

EID: 0036058081     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012631     Document Type: Article

References (10)

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2. A tutorial on built-in self-test, part 2: Applications
3. Testing embedded-core based system chips
4. On synthesis-for-testability of combinational logic circuits
5. Sequential circuit test generation using dynamic state traversal
6. PROPTEST: A property based test pattern generator for sequential circuits using test compaction
7. Vector restoration based static compaction of test sequences for synchronous sequential circuits