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Volumn 2005, Issue , 2005, Pages 1090-1098

X-filter: Filtering unknowns from compacted test responses

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTING CODES; TEST RESPONSE; X-FILTER;

EID: 33847150425     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584076     Document Type: Conference Paper
Times cited : (47)

References (26)
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  • 2
    • 1642273030 scopus 로고    scopus 로고
    • X-Compact: An Efficient Response Compaction Technique
    • March
    • S. Mitra and K.S. Kim, X-Compact: An Efficient Response Compaction Technique, IEEE Trans. CAD, Vol. 23, Issue 3, pp. 421-432, March 2004.
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  • 3
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    • Analysis and Design of Optimal Combinational Compactors
    • P. Wohl and L. Huisman, Analysis and Design of Optimal Combinational Compactors, Proc. IEEE VLSI Test Symp., pp. 101-106, 2003.
    • (2003) Proc. IEEE VLSI Test Symp , pp. 101-106
    • Wohl, P.1    Huisman, L.2
  • 10
    • 0032063899 scopus 로고    scopus 로고
    • Zero-aliasing space compaction using linear compactors with bounded overhead
    • May
    • K. Chakrabarty, Zero-aliasing space compaction using linear compactors with bounded overhead IEEE Trans. Computer-Aided Design, vol. 17, pp. 452-457, May 1998.
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    • Chakrabarty, K.1
  • 12
    • 0032310133 scopus 로고    scopus 로고
    • Synthesis of Zero-Aliasing Space Elementary-Tree Space Compactors
    • B. Pouya and N. Touba, Synthesis of Zero-Aliasing Space Elementary-Tree Space Compactors, Proc. IEEE VLSI Test Symp., pp. 70-77, 1998.
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    • Pouya, B.1    Touba, N.2
  • 13
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    • Efficient construction of aliasing-free compaction circuitry
    • Sept.-Oct
    • O. Sinanoglu, and A. Orailoglu Efficient construction of aliasing-free compaction circuitry IEEE Micro, Volume: 22, Issue: 5, pp. 82-92, Sept.-Oct. 2002
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 82-92
    • Sinanoglu, O.1    Orailoglu, A.2
  • 18
    • 0036446078 scopus 로고    scopus 로고
    • Embedded deterministic test for low cost manufacturing test
    • J. Rajski et al., Embedded deterministic test for low cost manufacturing test, Proc. IEEE International Test Conference, pp. 301-310, 2002.
    • (2002) Proc. IEEE International Test Conference , pp. 301-310
    • Rajski, J.1
  • 19
  • 21
    • 0043136599 scopus 로고    scopus 로고
    • Efficient compression and application of deterministic patterns in a logic BIST architecture
    • P. Wohl, J. A. Waicukauski, S. Patel, and M. B. Amin, Efficient compression and application of deterministic patterns in a logic BIST architecture, Proc. Design Automation Conf., pp. 566-569, 2003.
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  • 22
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    • Virtual Scan Chains: A Means for Reducing Scan Length in Cores
    • A. Jas, B. Pouya and N. A. Touba, Virtual Scan Chains: A Means for Reducing Scan Length in Cores, Proc. VLSI Test Symposium, pp. 73-78, 2000.
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  • 24
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    • Frequency-Directed Run Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.