Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance, and technological constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 8, 2009, Pages 1237-1250

  Weerasekera, Roshan ^a   Pamunuwa, Dinesh ^a   Zheng, Li Rong ^b   Tenhunen, Hannu ^b  

^a LANCASTER UNIVERSITY   (United Kingdom)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

3 D integration; Die stacking; Performance and cost tradeoffs; Power consumption; System in package (SiP); System on chip (SoC); System on package (SoP); Thermal analysis; Wafer level integration (WLI)

Indexed keywords

3-D INTEGRATION; DIE STACKING; PERFORMANCE AND COST TRADEOFFS; POWER CONSUMPTION; SYSTEM-IN-PACKAGE (SIP); SYSTEM-ON-CHIP (SOC); SYSTEM-ON-PACKAGE (SOP); THERMAL ANALYSIS; WAFER-LEVEL INTEGRATION (WLI);

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CELLULAR RADIO SYSTEMS; COMMUNICATION CHANNELS (INFORMATION THEORY); COST ACCOUNTING; COSTS; DIES; ELECTRIC POWER UTILIZATION; ELECTRONICS ENGINEERING; HAND HELD COMPUTERS; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SILICON WAFERS; SYSTEMS ANALYSIS; THERMOANALYSIS; THREE DIMENSIONAL;

COST BENEFIT ANALYSIS;

EID: 68549115318     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2021734     Document Type: Article

References (58)

1. F. Catthoor, N. D. Dutt, and C. E. Kozyrakis, "How to solve the current memory access and data transfer bottlenecks: At the processor architecture or at the compiler level," in Proc. Conf. Des., Autom. Test Eur., New York, 2000, pp. 426-435.
2. The International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: http://www.itrs.net/Links/2003ITRS/Home2003.htm
3. E. Beyne, "3D interconnection and packaging: Impending reality or still a dream?" in Proc. IEEE Int. Solid-State Circuits Conf., 2004, vol. 1, pp. 138-139.
4. M. Bamal, S. List, M. Stucchi, A. Verhulst, M. Van Hove, R. Cartuyvels, G. Beyer, and K. Maex, "Performance comparison of interconnect technology and architecture options for deep submicron technology nodes," in Proc. Int. Interconnect Technol. Conf., 2006, pp. 202-204.
5. S. Kim, C. Liu, L. Xue, and S. Tiwari, "Crosstalk reduction in mixed-signal 3-D integrated circuits with interdevice layer ground planes," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1459-1467, Jul. 2005.
6. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICS: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
7. B. Goplen and S. S. Sapatnekar, "Placement of thermal vias in 3-D ICs using various thermal objectives," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp. 692-709, Apr. 2006.
8. Z. Li, X. Hong, Q. Zhou, S. Zeng, J. Bian, W. Yu, H. H. Yang, V. Pitchumani, and C.-K. Cheng, "Efficient thermal via planning approach and its application in 3-D floorplanning," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 4, pp. 645-658, Apr. 2007.
9. J. M. Koo, S. Im, L. Jiang, and K. E. Goodson, "Integrated microchannel cooling for three-dimensional circuit architectures," J. Heat Transf., vol. 127, no. 1, pp. 49-58, Jan. 2005.
10. B. Dang, M. Bakir, and J. Meindl, "Integrated thermal-fluidic i/o interconnects for an on-chip microchannel heat sink," IEEE Electron Device Lett., vol. 27, no. 2, pp. 117-119, Feb. 2006.
11. M. Shen, L.-R. Zheng and H. Tenhunen, "Cost and performance analysis for mixed-signal system implementation: System-on-chip or system-on-package? " IEEE Trans. Electron. Packag. Manuf., vol. 25, no. 4, pp. 262- 272, Oct. 2002.
12. C. C. Liu, J.-H. Chen, R. Manohar, and S. Tiwari, "Mapping system-on-chip designs from 2-D to 3-D ICs," in Proc. IEEE Int. Symp. Circuits Syst., 2005, pp. 2939-2942.
13. P. Mercier, S. R. Singh, K. Iniewski, B. Moore, and P. O'Shea, "Yield and cost modeling for 3D chip stack technologies," in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2006, pp. 357-360.
14. R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, "Extending systems-on-chip to the third dimension: Performance, cost and technological tradeoffs," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 2007, pp. 212-219.
15. R. K. Ulrich and W. D. Brown, Eds., Advanced Electronic Packaging, 2nd ed., ser. IEEE Press Series on Microelectronic Systems. New York: Wiley-Interscience, Sep. 2005.
16. M. Dreiza, A. Yoshida, J. Micksch, and L. Smith, "Stacked package-on-package design guidelines," Chip Scale Rev., no. 7, Jul. 2005. [Online]. Available: http://www.chipscalereview.com/issues/ 0705/article.php?type=feature&article=f3
17. T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New three-dimensional integration technology using chip-to-wafer bonding to achieve ultimate super-chip integration," Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3030-3035, 2006.
18. E. Culurciello and A. G. Andreou, "Capacitive inter-chip data and power transfer for 3-D VLSI," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 12, pp. 1348-1352, Dec. 2006.
19. A. Fazzi, L. Magagni, M. Mirandola, R. Canegallo, S. Schmitz, and R. Guerrieri, "A 0.14 mW/Gbps high-density capacitive interface for 3D system integration," in Proc. IEEE Custom Integr. Circuits Conf., 2005, pp. 101-104.
20. J. Xu, J. Wilson, S. Mick, L. Luo, and P. Franzon, "2.8 Gb/s inductively coupled interconnect for 3D ICS," in Proc. Symp. VLSI Circuits, Dig. Tech. Papers, 2005, pp. 352-355.
21. A. Iwata, M. Sasaki, T. Kikkawa, S. Kameda, H. Ando, K. Kimoto, D. Arizono, and H. Sunami, "A 3D integration scheme utilizing wireless interconnections for implementing hyper brains," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 262-597.
22. H. B. Backoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
23. B. Geuskens and K. Rose, Modeling Microprocessor Performance. Norwell, MA: Kluwer, 1998.
24. D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 663-670, Jun. 1994.
25. V. Garg, D. Stogner, C. Ulmer, D. Schimmel, C. Dislis, S. Yalamanchili, and D. Wills, "Early analysis of cost/performance trade-offs in MCM systems," IEEE Trans. Compon., Packag., Manuf. Technol. B, Adv. Packag., vol. 20, no. 3, pp. 308-319, Aug. 1997.
26. 2PAL ) model," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 239-251, Feb. 2001.
27. R. Venkatesan, J. A. Davis, K. A. Bowman, and J. D. Meindl, "Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 6, pp. 899-912, Dec. 2001.
28. G. Sai-Halasz, "Performance trends in high-end processors," Proc. IEEE, vol. 83, no. 1, pp. 20-36, Jan. 1995.
29. Q. Chen, J. A. Davis, P. Zarkesh-Ha, and J. Meindl, "A compact physical via blockage model," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 6, pp. 689-692, Dec. 2000.
30. P. A. Sandborn and H. Moreno, Conceptual Design of Multichip Modules and Systems. Norwell, MA: Kluwer, 1994.
31. W. Donath, "Placement and average interconnection lengths of computer logic," IEEE Trans. Circuits Syst., vol. CAS-26, no. 4, pp. 272-277, Apr. 1979.
32. M. Feuer, "Connectivity of random logic," IEEE Trans. Comput., vol. C-31, no. 1, pp. 29-33, Jan. 1982.
33. W. R. Heller, C. G. Hsi, and W. F. Mikhaill, "Wirability - Designing wiring space for chips and chip packages," IEEE Des. Test Mag., vol. 1, no. 3, pp. 43-51, Aug. 1984.
34. J. A. Davis, V. K. De, and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 580-589, Mar. 1998.
35. P. Sandborn, M. Abadir, and C. Murphy, "The tradeoff between peripheral and area array bonding of components in multichip modules," IEEE Trans. Compon., Packag., Manuf. Technol., Part A, vol. 17, no. 2, pp. 249- 256, Jun. 1994.
36. P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, "Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 6, pp. 649- 659, Dec. 2000.
37. A. George, J. Krusius, and R. Granitz, "Packaging alternatives to large silicon chips: Tiled silicon on MCM and PWB substrates," IEEE Trans. Compon., Packag., Manuf. Technol., B: Adv. Packag., vol. 19, no. 4, pp. 699-708, Nov. 1996.
38. Y. Deng and W. P. Maly, "2.5-dimensional VLSI system integration," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 668- 677, Jun. 2005.
39. D. Ragan, P. Sandborn, and P. Stoaks, "A detailed cost model for concurrent use with hardware/software co-design," in Proc. 39th IEEE/ACM Des. Autom. Conf., 2002, pp. 269-274.
40. The International Technology Roadmap for Semiconductors (ITRS), 1999. [Online]. Available: http://www.itrs.net
41. S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," in IEDM Tech. Dig., 2000, pp. 727-730.
42. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. Stan, "HotSpot: A compact thermal modeling methodology for early-stage VLSI design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 5, pp. 501-513, May 2006.
43. G. Luca, B. Agrawal, N. Srivastava, S.-C. Lin, T. Sherwood, and K. Banerjee, "A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy," in Proc. Des. Autom. Conf., 2006, pp. 991-996.
44. H. Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, R. Jenkal, and W. Davis, "Exploring compromises among timing, power and temperature in three-dimensional integrated circuits," in Proc. Des. Autom. Conf., 2006, pp. 997-1002.
45. L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, "Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design," in Proc. Eur. Solid-State Circuits Conf., 2000, pp. 352-355.
46. D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, "Maximizing throughput over parallel wire structures in the deep submicrometer regime," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 2, pp. 224-243, Apr. 2003.
47. R. Weerasekera, D. Pamunuwa, L. Zheng, and H. Tenhunen, "Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 5, pp. 589-593, May 2008.
48. J. Ku and Y. Ismail, "Thermal-aware methodology for repeater insertion in low-power VLSI circuits," in Proc. Int. Symp. Low Power Electron. Des., 2007, pp. 86-91.
49. Y. Ku and J. C. Ismail, "On the scaling of temperature-dependent effects," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 10, pp. 1882-1888, Oct. 2007.
50. J. E. Sergent and A. Krum, Eds., Thermal Management Handbook for Electronic Assemblies. New York: McGraw-Hill, 1998.
51. Micron Technol., Inc., Micron CMOS Image Sensor Part Catalog, Boise, ID, Mar. 2007. [Online]. Available: http://www.micron.com
52. Micron Technol., Inc., Micron 128 MB SDRAM Part Catalog, Boise, ID, 2007. [Online]. Avaialble: http://www.micron.com
53. ARM Holdings PLC, ARM Cortex-A8 Processor Product Brief, Cambridge, NJ, Mar. 2007. [Online]. Avaialble: http://www.arm.com
54. E. Beyne, "The rise of the 3rd dimension for system intergration," in Proc. Int. Technol. Conf., 2006, pp. 1-5.
55. R. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," Proc. IEEE, vol. 94, no. 6, pp. 1214-1224, Jun. 2006.
56. R. Waiser Ed., Nanoelectronics and Information Technology: Advanced Electronic Materials and Novel Devices. Hoboken, NJ: Wiley-VCH, Sep. 2004.
57. S. Afonso, L. Schaper, J. Parkerson, W. Brown, S. Ang, and H. Naseem, "Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 309-320, Aug. 1999.
58. P. Mehrotra, V. Rao, T. M. Conte, and P. D. Franzon, "Optimal chip-package codesign for high-performance DSP," IEEE Trans. Adv. Packag., vol. 28, no. 2, pp. 288-297, May 2005.