A 3D integration scheme utilizing wireless interconnections for implementing hyper brains

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Iwata, Atsushi ^a   Sasaki, Mamoru ^a   Kikkawa, Takamaro ^a   Kameda, Seiji ^a   Ando, Hiroshi ^a   Kimoto, Kentaro ^a   Arizono, Daisuke ^a   Sunami, Hideo ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144448386     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. K. Kanda et al., "1.27Gb/s/ch 3mW/pin Wireless Super-connect (WSC) Interface Scheme," ISSCC Dig. Tech. Papers, pp. 186-187, Feb., 2003.
2. D. Mizoguchi et al. "A 1.2Gb/s/pin Wireless Superconnect Base on Inductive Inter-Chip Signaling (US)," ISSCC Dig.Tech. Papers, pp. 142-143, Feb., 2004.
3. A. Rashid et al., "High Transmission Gain Integrated Antenna on Extremely High Resistivity Si for ULSI Wireless Interconect," IEEE ED Letters, vol. 23, no. 12, pp. 731-733, Dec., 2002.