Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 6, 2000, Pages 649-659

  Zarkesh Ha, Payman ^a,b   Davis, Jeffrey A ^b   Meindl, James D ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GLOBAL INTERCONNECT; MINIMUM RECTILINEAR STEINER TREE; PLACEMENT MODEL; RENT RULE; SYSTEM-ON-A-CHIP;

COMPUTER AIDED DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; RANDOM PROCESSES; TREES (MATHEMATICS);

INTEGRATED CIRCUIT LAYOUT;

EID: 0034459340     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.902259     Document Type: Article

References (24)

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