Optimal chip-package codesign for high-performance DSP

IEEE Transactions on Advanced Packaging

Volumn 28, Issue 2, 2005, Pages 288-297

  Mehrotra, Pronita ^a,b   Rao, Vikram ^a,c   Conte, Thomas M ^a   Franzon, Paul D ^a  

^a North Carolina State University   (United States)

^b Sun Microsystems ^*

^c SUN MICROSYSTEMS   (United States)

Author keywords

Chip package codesign; Fast Fourier transform (FFT); Seamless high off chip connectivity (SHOCC)

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; DYNAMIC RANDOM ACCESS STORAGE; FAST FOURIER TRANSFORMS; FLIP CHIP DEVICES; MATHEMATICAL MODELS; MULTICHIP MODULES; SUBSTRATES; TRANSMISSION LINE THEORY;

CHIP PACKAGE CODESIGN; SEAMLESS HIGH OFF-CHIP CONNECTIVITY (SHOCC);

CHIP SCALE PACKAGES;

EID: 20344404718     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2005.846937     Document Type: Article

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