Thermal-aware methodology for repeater insertion in low-power VLSI circuits

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 86-91

  Ku, Ja Chun ^a   Ismail, Yehea ^a  

^a Northwestern University   (United States)

Author keywords

Low power design; Repeater insertion; Temperature aware design

Indexed keywords

LOW POWER DESIGN; REPEATER INSERTION; TEMPERATURE AWARE DESIGN;

COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; ENERGY DISSIPATION; TELECOMMUNICATION REPEATERS; THERMAL EFFECTS; VLSI CIRCUITS;

CIRCUIT THEORY;

EID: 36949010547     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283799     Document Type: Conference Paper

References (19)

1. International Technology Roadmap for Semiconductors, 2005.
2. D. Sylvester and K. Keutzer, "A global wiring paradigm for deep submicron design," in IEEE Trans. CAD, vol. 19, pp. 242-252, Feb. 2000.
3. K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," in IEEE Trans. Electronic Devices, vol. 49, pp. 2001-2007, Nov. 2002.
4. P. Kapur, G. Chandra, C. Saraswat, "Power estimation in global interconnects and its reduction using a novel repeater optimization methodology," in Proc. DAC, pp. 461-466, Jun. 2002.
5. X. Liu, Y. Peng, M. Papaefthymiou, "Practical repeater insertion for low power: what repeater library do we need?," in Proc. DAC, pp. 30-35, Jun. 2004.
6. V. Wason and K. Banerjee, "A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variation," in Proc. ISLPED, pp. 131-136, Aug. 2005.
7. K. Banerjee, S. Lin, A. Keshavarzi, S. Narendra, and V. De, "A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management," in Proc. IEDM, pp. 887-890, Dec. 2003.
8. L. He, W. Liao, and M. Stan, "System level leakage reduction considering the interdependence of temperature and leakage," in Proc. DAC, pp. 12-17, Jun. 2004.
9. W. Huang, E. Humenay, K. Skadron, and M. Stan, "The need for a full-chip and package thermal model for thermally optimized IC designs," in Proc. ISLPED, pp. 245-250, Aug. 2005.
10. M. Mui, K. Banerjee, and A. Mehrotra, "Supply and power optimization in leakage-dominant technologies," in IEEE Trans. CAD, vol. 24, pp. 1362-1371, Sep. 2005.
11. H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. MA: Addision-Wesley, 1990.
12. T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas," in IEEE J. Solid-State Circuits, vol. 25, pp. 584-593, Apr. 1990.
13. J. Daga, E. Ottaviano, D. Auvergne, "Temperature effect on delay for low voltage applications," in Proc. DATE, pp. 680-685, 1998.
14. C. Park et al., "Reversal of temperature dependence of integrated circuits operating at very low voltages," in Proc. IEDM, pp. 71-74, 1995.
15. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. CICC, pp. 201-204, 2000. (http://www.eas.asu.edu/ ~ptm)
16. K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," in Proc. IEEE, vol. 91, pp. 305-327, Feb. 2003.
17. Y. Taur and T. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, 1998.
18. H. Su, F. Liu, A. Devgan, E. Acar, S. Nassif, "Full chip leakage estimation considering power supply and temperature variations," in Proc. ISLPED, pp. 78-83, Aug. 2003.
19. A. Chapman, Fundamentals of heat transfer. Macmillan Press, 1987.