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Volumn , Issue , 2006, Pages 997-1002

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits

Author keywords

3DIC; Design flow; Temperature dependency; Trade off

Indexed keywords

ELECTRIC POWER SYSTEMS; HIGH DEFINITION TELEVISION; INTERCONNECTION NETWORKS; LEAKAGE CURRENTS;

EID: 34547151747     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147161     Document Type: Conference Paper
Times cited : (31)

References (22)
  • 1
    • 0025475660 scopus 로고
    • Temperature Dependence of Threshold Voltage in Thin-Film SOI MOSFET's
    • Aug
    • G. Groeseneken, et al"Temperature Dependence of Threshold Voltage in Thin-Film SOI MOSFET's", IEDL, Vol. 11, No. 8, Aug. 1990.
    • (1990) IEDL , vol.11 , Issue.8
    • Groeseneken, G.1
  • 2
    • 85088341156 scopus 로고    scopus 로고
    • Full Chip Leakage Estimation Considering Power Supply and Temperature Variations
    • Aug
    • H. Su, F. Liu, A. Devgan, E. Acar and S. Nassif, "Full Chip Leakage Estimation Considering Power Supply and Temperature Variations", ISLPED, Aug. 2003.
    • (2003) ISLPED
    • Su, H.1    Liu, F.2    Devgan, A.3    Acar, E.4    Nassif, S.5
  • 3
    • 22544456242 scopus 로고    scopus 로고
    • Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level
    • Jul
    • W. Liao, L. He and K. M. Lepak, "Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level", TCAD, Vol. 24, No. 7, Jul. 2005.
    • (2005) TCAD , vol.24 , Issue.7
    • Liao, W.1    He, L.2    Lepak, K.M.3
  • 4
    • 85001141006 scopus 로고    scopus 로고
    • Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)
    • June
    • A. Rahman, A. Fan and R. Reif, "Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)", IITC, June 2001.
    • (2001) IITC
    • Rahman, A.1    Fan, A.2    Reif, R.3
  • 5
    • 28344443452 scopus 로고    scopus 로고
    • Thermal Via Placement in 3D ICs
    • B. Goplen and S. Sapatnekar, "Thermal Via Placement in 3D ICs", ISPD, 2005.
    • (2005) ISPD
    • Goplen, B.1    Sapatnekar, S.2
  • 6
    • 33751410351 scopus 로고    scopus 로고
    • Thermal via Planning for 3-D ICs
    • Nov
    • J. Cong and Y. Zhang, "Thermal via Planning for 3-D ICs", ICCAD, Nov. 2005.
    • (2005) ICCAD
    • Cong, J.1    Zhang, Y.2
  • 7
    • 84948451001 scopus 로고    scopus 로고
    • A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits
    • Mar
    • S. M. Alam, D.E. Troxel and C.V. Thompson, "A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits" ISQED, Mar. 2002.
    • (2002) ISQED
    • Alam, S.M.1    Troxel, D.E.2    Thompson, C.V.3
  • 8
    • 0347409236 scopus 로고    scopus 로고
    • Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
    • Nov
    • B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach," ICCAD, Nov. 2003.
    • (2003) ICCAD
    • Goplen, B.1    Sapatnekar, S.2
  • 9
    • 16244385917 scopus 로고    scopus 로고
    • A Thermal-Driven Floorplanning Algorithm for 3D ICs
    • Nov
    • J. Cong, W. Jie and Z. Yan, "A Thermal-Driven Floorplanning Algorithm for 3D ICs", ICCAD, Nov. 2004.
    • (2004) ICCAD
    • Cong, J.1    Jie, W.2    Yan, Z.3
  • 10
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
    • May
    • K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat, "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration", Proceedings of the IEEE, May 2001.
    • (2001) Proceedings of the IEEE
    • Banerjee, K.1    Souri, S.J.2    Kapur, P.3    Saraswat, K.C.4
  • 11
    • 85165865615 scopus 로고    scopus 로고
    • A. Bellaouar A., A. Fridi, M. J. Elmasry and K. Itoh, Supply voltage scaling for temperature insensitive CMOS circuit operation. TCAS II, Mar 1998.
    • A. Bellaouar A., A. Fridi, M. J. Elmasry and K. Itoh, "Supply voltage scaling for temperature insensitive CMOS circuit operation". TCAS II, Mar 1998.
  • 12
    • 0034452632 scopus 로고    scopus 로고
    • Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs
    • S. Im and Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs", IEDM 2000.
    • (2000) IEDM
    • Im, S.1    Banerjee2
  • 13
    • 0035208728 scopus 로고    scopus 로고
    • Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
    • Nov
    • T. Y. Chiang, K. Banerjee and K. C. Saraswat, "Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects", ICCAD, Nov. 2001.
    • (2001) ICCAD
    • Chiang, T.Y.1    Banerjee, K.2    Saraswat, K.C.3
  • 14
    • 0035473305 scopus 로고    scopus 로고
    • Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs
    • Oct
    • K. Kanda, K. Nose, H. Kawaguchi and T. Sakurai "Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs". JSSCC, Oct. 2001.
    • (2001) JSSCC
    • Kanda, K.1    Nose, K.2    Kawaguchi, H.3    Sakurai, T.4
  • 15
    • 28344439387 scopus 로고    scopus 로고
    • Power trends and performance characterization of 3-dimensional integration for future technology generations
    • Mar
    • R. Zhang, K. Roy, Cheng-Kok Koh, D.B. Janes, "Power trends and performance characterization of 3-dimensional integration for future technology generations", ISQED, Mar. 2001.
    • (2001) ISQED
    • Zhang, R.1    Roy, K.2    Cheng-Kok Koh, D.B.3    Janes4
  • 16
    • 84954424983 scopus 로고    scopus 로고
    • Design tools for 3-D integrated circuits
    • Jan
    • S. Das, A. Chandrakasan and R. Reif, "Design tools for 3-D integrated circuits", ASP-DAC, Jan. 2003.
    • (2003) ASP-DAC
    • Das, S.1    Chandrakasan, A.2    Reif, R.3
  • 17
    • 17644378782 scopus 로고    scopus 로고
    • 3D processing technology and its impact on iA32 microprocessors
    • Oct
    • B. Black, D.W. Nelson, C. Webb and N. Samra, "3D processing technology and its impact on iA32 microprocessors", ICCD, Oct. 2004.
    • (2004) ICCD
    • Black, B.1    Nelson, D.W.2    Webb, C.3    Samra, N.4
  • 19
    • 28344452134 scopus 로고    scopus 로고
    • Demystifying 3D ICs: The pros and cons of going vertical
    • Nov.-Dec
    • W. R. Davis et al, "Demystifying 3D ICs: the pros and cons of going vertical," IEEE Design & Test of Computers, vol 22, no 6, Nov.-Dec. 2005.
    • (2005) IEEE Design & Test of Computers , vol.22 , Issue.6
    • Davis, W.R.1
  • 21
    • 28144458334 scopus 로고    scopus 로고
    • Megapixel CMOS Image Sensor Fabrication in Three-Dimensional Integrated Circuit Technology
    • Feb
    • V. Suntharalingam et al, "Megapixel CMOS Image Sensor Fabrication in Three-Dimensional Integrated Circuit Technology", ISSCC, Feb. 2005.
    • (2005) ISSCC
    • Suntharalingam, V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.