Mapping system-on-chip designs from 2-D to 3-D ICs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2939-2942

  Liu, Christianto C ^a   Chen, Jeng Huei ^a   Manohar, Rajit ^a   Tiwari, Sandip ^a  

^a School of Chemical and Molecular Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; CHIP AREAS; CRITICAL ISSUES; GLOBAL INTERCONNECT DELAY; GLOBAL WIRES; HEAT DISSIPATION; MANUFACTURING COST; MAPPING SYSTEMS; ON-CHIP TEMPERATURE; SOC DESIGNS; SYSTEM ON CHIP DESIGN; THREE DIMENSIONAL INTEGRATED CIRCUITS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; THREE DIMENSIONAL;

MULTIMEDIA SYSTEMS;

EID: 50249151517     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465243     Document Type: Conference Paper

References (18)

1. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," IEEE Computer, vol. 35, pp. 70-78, Jan. 2002.
2. K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE, vol. 89, May 2001, pp. 602-633.
3. M. Ohmura, "An initial placement algorithm for 3-D VLSI," Int. Symposium on Circuits and Systems, vol. 6, pp. 195-198, June 1998.
4. T. Tanprasert, "An analytical 3-D placement that reserves routing space," Int. Symposium on Circuits and Systems, vol. 3, pp. 69-72, May 2000.
5. Y. S. Deng and W. Maly, "Physical design of the "2.5D" stacked system," Int. Conf. on Computer Design, pp. 211-217, Oct. 2003.
6. I. Kaya, M. Olbrich, and E. Barke, "3-D placement considering vertical interconnects," SOC Conf., pp. 257-258, Sept. 2003.
7. B. Goplen and S. Sapatnekar, "Efficient thermal placement of standard cells in 3D ICs using a force directed approach," Int. Conf. on Computer Aided Design, pp. 86-89, Nov. 2003.
8. A. Sai-Halasz, "Performance trends in high-end processors," Proceedings of the IEEE, vol. 83, pp. 20-36, Jan. 1995.
9. N. Sherwani. Algorithms for VLSI Physical Design Automation. Norwell, MA: Kluwer, 1999.
10. G. Chandra, P. Kapur, and K. C. Saraswat, "Scaling trends for the on chip power dissipation," Int. Interconnect Technology Conf., pp. 170- 172, June 2002.
11. MITLL Low-Power FDSOI CMOS Process: Design Guide. (2004, Nov.). Process version: 3D01.
12. S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," Int. Electron Devices Meeting, pp. 727-730, Dec. 2000.
13. Alain J. Martin , Mika Nyström, and Paul I. Pénzes. ET2: a metric for time and energy efficiency of computation, Power aware computing. Norwell, MA: Kluwer Academic Publishers, 2002.
14. T. Wang. Global Optimization for Constrained Nonlinear Programming. Ph.D. Dissertation, University of Illinois at Urbana- Champaign, 2001.
15. C. Sechen and A. Sangiovanni-Vincentelli, "The TimberWolf placement and routing package," IEEE Journal of Solid-State Circuits, vol. 20, pp. 510-522, Apr. 1985.
16. International Technology Roadmap for Semiconductors: International SEMATECH, 2003.
17. E. G. T. Jaspers and P. H. N. de With, "Chip-set for video display of multimedia information," IEEE Trans. on Consumer Electronics, vol. 45, August 1999.
18. D. Altavilla. (2002, Aug.). The ATi Radeon 9700 Pro full release review. [Online]. Available: http://www.hothardware.com/hh-files/ S&V/radeon9700pro. shtml