How to solve the current memory access and data transfer bottlenecks: At the processor architecture or at the compiler level?

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 426-433

  Catthoor, Francky ^a   Dutt, Nikil D ^b   Kozyrakis, Christoforos E ^c  

^a IMEC   (Belgium)

^b UCBerkeley CA ^*

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT PROCESSORS; DATA ACCESS; DATA THROUGHPUT; HIGHLY PARALLELS; MEMORY ACCESS; NOVEL SOLUTIONS; PROCESSOR ARCHITECTURES; TRANSFER BOTTLENECKS;

COMPUTER ARCHITECTURE; DATA TRANSFER; EXHIBITIONS; PROGRAM COMPILERS;

CACHE MEMORY;

EID: 84893701166     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840306     Document Type: Conference Paper

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