Yield and cost modeling for 3D chip stack technologies

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 357-360

  Mercier, P ^a   Singh, S R ^a   Iniewski, K ^a   Moore, B ^b   O'Shea, P ^c  

^a UNIVERSITY OF ALBERTA   (Canada)

^b BigBangwidth   (Canada)

^c PMC Sierra Ltd Burnaby   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; INTEGRATED CIRCUIT MANUFACTURE; THREE DIMENSIONAL;

CHIP ARRAY; CHIP STACK TECHNOLOGIES; SYSTEM PERFORMANCE;

CHIP SCALE PACKAGES;

EID: 39049113371     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320948     Document Type: Conference Paper

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