SCOPUS 정보 검색 플랫폼

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 352-355

Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design

(3) Zheng, Li Rong a Pamunuwa, Dinesh a Tenhunen, Hannu a

a ROYAL INSTITUTE OF TECHNOLOGY (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUB-MICRON; DEEP SUB-MICRON TECHNOLOGY; DELAY ESTIMATION; ELECTROMAGNETIC SIMULATION; INTERCONNECT MODELING; SIGNAL INTEGRITY; TIME EFFICIENCIES; VLSI DESIGN;

EID: 0041297627 PISSN: 19308833 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (6)

References (9)

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2
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- Chiprout, E.¹

3
- 0008405647
- A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation
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- Lee, M.¹

4
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- Multilevel metal capacitance models for CAD design synthesis systems
- J. H.Chen, J. Huang, L. Arledge, P.C.Li, and P. Yang, "Multilevel metal capacitance models for CAD design synthesis systems," IEEE EDL-13, pp.32-34, 1992
- (1992) IEEE EDL-13 , pp. 32-34
- Chen, J.H.¹ Huang, J.² Arledge, L.³ Li, P.C.⁴ Yang, P.⁵

5
- 0021472075
- An analysis of interconnect line capacitance and coupling for VLSI circuits
- E. T. Lewis, "An analysis of interconnect line capacitance and coupling for VLSI circuits," Solid-State Electron., vol.27, pp.742-749, 1984
- (1984) Solid-State Electron. , vol.27 , pp. 742-749
- Lewis, E.T.¹

6
- 0020704286
- Simple formulas for two-and three-dimensional capacitance
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7
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- Interconnect and substrate modeling and analysis: An overview
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- Chiprout, E.¹

8
- 0008363830
- Noise margin constraint for interconnectivity in deep submicron low power and mixedsignal VLSI circuits
- L.-R. Zheng, H. Tenhunen, "Noise margin constraint for interconnectivity in deep submicron low power and mixedsignal VLSI circuits," in Proc. ARVLSI, pp.123-136, 1999
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- Zheng, L.-R.¹ Tenhunen, H.²

9
- 0008389652
- Global interconnect design for high speed ULSI and system-on-package
- L.-R. Zheng, B. X. Li, H. Tenhunen, "Global interconnect design for high speed ULSI and system-on-package," in Proc. IEEE ASIC/SOC conference, pp.251-256, 1999
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.