Advanced modeling and accurate characterization of a 16 Gb/s memory interface

IEEE Transactions on Advanced Packaging

Volumn 32, Issue 2, 2009, Pages 306-327

  Beyene, Wendemagegnehu ^a   Madden, Chis ^a   Chun, Jung Hoon ^a,b   Lee, Haechang ^a   Frans, Yohan ^a   Leibowitz, Brain ^a   Chang, Ken ^a   Kim, Namhoon ^a,c   Wu, Ting ^a   Yip, Gary ^a   Perego, Rich ^a  

^a RAMBUS INC   (United States)

^b Sungkyunkwan University   (South Korea)

^c XILINX INC   (United States)

Author keywords

Asymmetric interface; Bit error rate (BER); Clocks; De embedding; High speed link; IEEE; Integrated circuit interconnections; Integrated circuit modeling; Memory interface; Modeling; Multi gigahertz system; Random access memory; Receivers

Indexed keywords

ASYMMETRIC INTERFACE; BIT-ERROR-RATE (BER); DE-EMBEDDING; HIGH-SPEED LINK; IEEE; INTEGRATED CIRCUIT INTERCONNECTIONS; INTEGRATED CIRCUIT MODELING; MEMORY INTERFACE; MODELING; MULTI-GIGAHERTZ SYSTEM; RANDOM ACCESS MEMORY; RECEIVERS;

DIELECTRIC LOSSES; INTEGRATED CIRCUITS; METHOD OF MOMENTS; OPTICAL COMMUNICATION; RANDOM ACCESS STORAGE; SIGNAL RECEIVERS; SIMULATORS; SPEED; SURFACE ROUGHNESS; TIME DOMAIN ANALYSIS;

BIT ERROR RATE;

EID: 67349112710     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2009.2018460     Document Type: Article

References (54)

1. K. Chang et al., "A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface," in IEEE Symp. VLSI Circuits, Jun. 18-20, 2008, pp. 126-127.
2. N. Nguyen et al., "A 16-Gb/s differential I/O cell with 380 fs RJ in an emulated 40 nm DRAM process," in IEEE Symp. VLSI Circuits, Jun. 18-20, 2008, pp. 128-129.
3. W. T. Beyene et al., "Design and analysis of a TB/sec memory system," in Proc. IEEE 17th Topical Meeting Electrical Performance Electrical Packag. (EPEP), San Jose, CA, Oct. 27-29, 2008, pp. 21-24.
4. H. Lee et al., "A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface," J. Solid-State Circuits, vol. 44, no. 4, pp. 1235-1247, Sep. 2009.
5. T. Wu et al., "Clocking circuits for a 16 Gb/s memory interface," in IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 435- 438.
6. J. Chun et al., "A 16 Gb/s 65 nm CMOS tranceiver for a memory interface," in IEEE Asian Solid-State Circuits Conf., Fukuoka, Japan, Nov. 3-5, 2008, pp. 25-28.
7. D. B. Kuznetsov and J. E. Schutt-Ainé, "Optimal transient simulation of transmission lines," IEEE Trans. Circuits Syst.-I: Fundamental Theory Appl., vol. 43, no. 2, pp. 110-121, Feb. 1996.
8. R. Achar and M. S. Nakhla, "Simulation of high-speed interconnects," Proc. IEEE, vol. 89, no. 5, pp. 693-728, May 2001.
9. A. E. Ruehli and A. C. Cangellaris, "Progress in the methodologies for the electrical modeling of interconnects and electronic packages," Proc. IEEE, vol. 89, no. 5, pp. 740-771, May 2001.
10. A. Deutsch et al., "Prediction of losses caused by roughness of metallization in printed-circuit boards," Proc. IEEE, vol. 30, no. 2, pp. 279-287, May 2007.
11. J. Schutt-Ainé and R. Mittra, "Scattering parameter transient analysis of transmission lines loaded with nonlinear terminations," IEEE Trans. Microwave Theory Tech., vol. 36, no. 3, pp. 529-536, Mar. 1988.
12. Agilent Advanced Design System User's Guide. Santa Rosa, CA: Agilent Technologies, Feb. 2001.
13. M. Matoglu, M. Swaminathan, N. Pham, D. N. de Araujo, and M. Cases, "Efficient statistical analysis and diagnosis of high speed source synchronous interfaces," in Proc. IEEE 11th Topical Meeting Electrical Performance of Electron. Packag., Monterey, CA, Oct. 2002, pp. 223-226.
14. W. T. Beyene et al., "Application of artificial neural networks for efficient hardware characterization of high-speed interconnect systems," in Proc. IEEE 14th Topical Meeting Electrical Performance Electrical Packag. (EPEP), Austin, TX, Oct. 24-26, 2005, pp. 91-94.
15. W. T. Beyene, "Application of artificial neural networks to statistical analysis and nonlinear modeling of high-speed interconnect systems," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 26, no. 1, pp. 166-176, Jan. 2007.
16. A. R. Djordjevic, M. B. Bazdar, T. K. Sarkar, and R. F. Harrington, LINPAR for Windows, Version 2.0, Software and Users Manual. Boston, MA: Artech House, 1999.
17. User's Guide, Ansoft High Frequency Structure Simulator. Pittsburgh, PA: Ansoft, 1999.
18. W. T. Beyene et al., "System performance comparisons of coreless and standard packages for data rate beyond 20 Gbps," in Proc. 58th Electron. Compon. Technol. Conf., Lake Buena, FL, May 27-30, 2008, pp. 526-532.
19. H. Shi, J. Feng, W. Beyene, and C. Yuan, "A robust physical model extraction method for a memory device with differential routed package traces," in Proc. IEEE 13th Topical Meeting Electrical Performance Electrical Packag. (EPEP), Portland, OR, Oct. 25-27, 2004, pp. 135-138.
20. W. T. Beyene, N. Cheng, J. Feng, H. Shi, and C. Yuan, "Performance analysis of multi-gigahertz parallel bus with transmit pre-emphasis equalization," IEEE Trans. Microwave Theory Tech., vol. MTT-53, no. 11, pp. 3568-3577, Nov. 2005.
21. E. Säckinger and W. C. Fischer, "A 3-GHz 32-dB CMOS limiting amplifier for SONNET OC-48 receivers," J. Solid-State Circuits, vol. 35, no. 12, pp. 1884-1888, Dec. 2000.
22. R. Farjad-Rad et al., "0.622-8.0 Gbps 150mWserial IO macrocell with fully flexible preemphasis and equalization," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 63-66.
23. S. Gondi and B. Razavi, "Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receiver," J. Solid-State Circuits, vol. 42, no. 9, Sep. 2007.
24. L. Zhang et al., "Low power passive equalizer design for computer memory links," in Proc. 2008 16th IEEE Symp. High Performance Interconnects, Aug. 26-28, 2008, pp. 51-56.
25. B. Casper et al., "An 8-Gb/s simultaneous bidirectional link with on-die waveform capture," J. Solid-State Circuits, vol. 38, no. 12, pp. 2111-2120, Dec. 2003.
26. Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura, and T. Kuroda, "A 10 Gb/s receiver w/equalizer and on-chip monitor in 0.11 um CMOS," J. Solid-State Circuits, vol. 40, no. 4, Apr. 2005.
27. A. Heltbrog, I. Pollock, and R. Van Epps, "High-speed probe interconnect technique," presented at the DesignCon 2008, Santa Clara, CA, Feb. 4-7, 2008.
28. G. W. Roberts, "Improving the testability of mixed-signal integrated circuits," in Proc. Int. Custom Integrated Circuits Conf., 1997, pp. 214-221.
29. R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. Horowitz, "Applications of on-chip samplers for test and measurement of integrated circuits," in Proc. Symp. VLSI Circuits Dig. Tech. Papers 1998, pp. 138-139.
30. Y. Zheng. and K. L. Shepard, "On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits," IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 11, no. 3, pp. 336-344, Jun. 2003.
31. B. Casper and F. O'Mahony, "Clocking analysis, implementation and measurement techniques for high-speed data link a tutorial," IEEE Trans. Circuits Syst.-I: Regular Papers, vol. 56, no. 1, pp. 17-39, Jan. 2009.
32. K. Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizers May 2003 Online. Available: http://www.desingers-guide.com
33. M. H. Perrott, M. D. Trott, and C. G. Sodini, "A modeling approach for fractional-N frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002.
34. X. Mao, H. Yang, and H. Wang, "Behavioral modeling and simulation of jitter and phase noise in fractional-N PLL frequency synthesizer," in IEEE Int. Behavioral Modeling Simulation Conf., San Jos, CA, Oct. 2004, pp. 25-30.
35. J. Buckwalter, B. Analui, and A. Hajimiri, "Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects," in IEEE MTT-S Int. Microwave Symp. Dig., FortWorth, TX, Jun. 6-11, 2004, pp. 1627-1630.
36. S. Chaudhuri et al., "Jitter amplification characterization of passive clock channels at 6.4 and 9.6 Gb/s," in Proc. IEEE 15th Topical Meeting Electrical Performance Electronic Packag., Scottsdale, AZ, Oct. 23-25, 2006, pp. 21-24.
37. C. Madden et al., "Jitter amplification considerations for PCB clock channel design," in Proc. IEEE 16th Topical Meeting Electrical Performance Electron. Packag., Atlanta, GA, Oct. 2007, pp. 135-138.
38. G. Balamurugan and N. Shanghag, "Modeling and mitigation of jitter in multi-Gbps source-synchronous IO links," in Proc. 21st Int. Conf. Comput. Design, San Jose, CA, Oct. 13-15, 2003, pp. 254-260.
39. W. Beyene, "Modeling and analysis of jitter enhancement across high-speed interconnect systems," in Proc. IEEE 16th Topical Meeting Electrical Performance Electron. Packag., Atlanta, GA, Oct. 29-31, 2007, pp. 29-32.
40. R. Stephens, Jitter analysis: The dual-dirac model, RJ/DJ, and Q-scale Online. Available: http://cp.literature.agilent.com/litweb/pdf/5989- 3206EN.pdf Dec. 2004
41. T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T. Morf, J. Weiss, and M. L. Schmatz, "A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology," IEEE J. Solid-State Circuits, vol. 41, pp. 954-965, Apr. 2006.
42. M. Jeeradit, J. Kim, B. S. Leibowitz, P. Nikaeen, V.Wang, B. Garlepp, and C.Werner, "Characterizing sampling aperture of clocked comparators," in Dig. Tech. Papers, 2008 Symp. VLSI Circuits, Jun. 2008, pp. 68-69.
43. B. S. Leibowitz et al., "Characterization of random decision errors in clocked comparators," in IEEE CICC, San Jose, CA, Sep. 2008, pp. 691-694.
44. MATLAB Userś Guide. Natick, MA: MathWorks, Inc., 2000.
45. VHDL-AMS Language Reference Manual, IEEE Standard No.:1076.1-1999.
46. Verlog-A Language Reference Manual. Los Gatos, CA: Open Verilog International, 1996.
47. V. Stojanovic, "Channel limited high-speed links: Modeling, analysis and design," Ph.D. dissertation, Stanford Univ., Stanford, CA, 2004.
48. V. Stojanovic and M. Horowitz, "Modeling and analysis of high-speed links," in IEEE Custom Integrated Circuit Conf., 2003, pp. 589-594.
49. B. Ahmad and J. Cain, "Performance evaluation of high speed serial links," presented at the DesignCon 2001, Santa Clara, Jan./Feb. 2001.
50. B. K. Casper et al., "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes," in IEEE Symp. VLSI Circuits, Jun. 2002, pp. 54-57.
51. S. Sercu and J. D. Geest, "BER link simulations," presented at the DesignCon 2003, Santa Clara, CA, Jan. 27-30, 2003.
52. A. Sanders, M. Resso, and J. D'Ambrosia, "Channel compliance testing utilizing novel statistical eye methodology," presented at the DesignCon 2004, Santa Clara, CA, Feb. 2-5, 2004.
53. B. Casper et al., "Future microprocessor interfaces: Analysis, design and optimization," in IEEE Custom Integrated Circuit Conf. Sep. 2007, pp. 479-486.
54. D. Oh et al., "Accurate system voltage and timing margin simulation in high-speed I/O system design," IEEE Trans. Adv. Packag., vol. 31, no. 4, pp. 722-730, Nov. 2008.