A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 4, 2005, Pages 986-993

  Tomita, Yasumoto ^a   Kibune, Masaya ^b   Ogawa, Junji ^c   Walker, William W ^c   Tamura, Hirotaka ^b   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

^c FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Clock and data recovery (CDR); CMOS; Equalizer; Intersymbol interference (ISI); Receiver

Indexed keywords

BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; DIELECTRIC LOSSES; ELECTRIC CLOCKS; ENERGY UTILIZATION; EQUALIZERS; INTERSYMBOL INTERFERENCE; MICROPROCESSOR CHIPS; SERVERS; SKIN EFFECT; SWITCHES; VLSI CIRCUITS;

CLOCK AND DATA RECOVERY (CDR); CLOCK RECOVERY UNITS (CRU); OFF-CHIP CAPACITORS; SERIES EQUALIZERS;

SIGNAL RECEIVERS;

EID: 18744403118     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.845563     Document Type: Conference Paper

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