System performance comparisons of coreless and standard packages for data rate beyond 20 Gbps

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2008, Pages 526-532

  Beyene, Wendemagegnehu T ^a   Schmitt, Ralf ^a   Shi, Hao ^a   Feng, June ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; ERROR ANALYSIS; SIGNAL PROCESSING; SPEED; STANDARDS; STATISTICAL METHODS; SYSTEMS ENGINEERING;

DATA RATES; ELECTRONIC COMPONENTS; SYSTEM PERFORMANCES;

BIT ERROR RATE;

EID: 51349149016     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550023     Document Type: Conference Paper

References (13)

1. W. T. Beyene, C. Yuan, R. Dhat, and D. Seeker, "Effects of plating stubs on the electrical performance of wirebond PBGA packages," Proceedings of the International Conference on Advanced Packaging and Systems, Reno, NA, pp. 25-30, March 10-13, 2002.
2. R. Sung, K. Chiang, Y. P. Wang, C.S. Hsiao, "Comparative analysis of electrical performance on coreless and standard flip-chip substrate," Proceedings of Electrical Components and Technology Conference, Reno, NA, pp. 1921-1924, May 29-June 1, 2007.
3. J. Sakai,T. Shimoto, K. Nakase, H. Inoue, K. Motonaga, H. Honda, "Signal integrity and power integrity properties of FCBGA based on ultra-thin, high density package substrate," Proceedings of Electrical Components and Technology Conference, Lake Buena Vista, FL, pp. 284-290, May 31-June 3, 2005.
4. Djordjevic, M. B. Bazdar, T. Sarkar, and R. Harrington, LINPAR for Windows, version 2.0, Software and User's Manual, Boston: Artech House, Inc, 1999..
5. Ansoft High Frequency Structure Simulator, Ansoft, 1999.
6. Agilent Advanced Design System User's Guide, Agilent Technologies, February 2001, Agilent Technologies, Santa Rosa, CA.
7. HSPICE Simulation and Analysis User Guide, Release U-2003.03-PA, March 2003
8. A. Sanders, M. Resso, and J. D'Ambrosia, "Channel compliance testing utilizing novel statistical eye methodology," DesignCon, February 2004.
9. V. Stojanovic, Channel Limited High-Speed Links: Modeling, Analysis and Design, PhD Thesis, Stanford University, 2004
10. B. Ahmad, "Performance Specification of interconnect", DesignCon, February 2003.
11. M. Swaminatan and A. E. Engin, Power Integrity Modeling and Design for Seminconductors and Systems, Prentice-Hall (Boston, MA 2007).
12. th Topical Meeting on Electrical Performance of Electronic Packages, pp 141-144, Princeton, 2003.
13. R. Schmitt, C. Yuan, "Power Distribution Design Considerations and Methodology for Multi-Gigabit I/Os", Proceedings IEEE Internaltional Symposium on Electromagnetic Compatibility, pp 660-665, Chicago, 2005.