Behavioral modeling and simulation of jitter and phase noise in fractional-N PLL frequency synthesizer

BMAS 2004 - Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference

Volumn , Issue , 2004, Pages 25-30

  Mao, Xiaojian ^a   Yang, Huazhong ^a   Wang, Huf ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; JITTER; MATHEMATICAL MODELS; PHASE LOCKED LOOPS; SPECTRUM ANALYSIS; SPURIOUS SIGNAL NOISE;

BEHAVIORAL MODELS; GAUSSIAN PROCESS; PHASE NOISE; VOLTAGE DOMAIN MODELS;

FREQUENCY SYNTHESIZERS;

EID: 15944393497     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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4. K, Kundert, "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers," Available from www.desineers-guide.com. May, 2003.
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8. A. Demir, E. Liu, and A. Sangiovanni-Vincentelli, "Time-domain non-Monte-Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.15, no. 5, pp. 493-505, May 1996.
9. Verilog-A Language Reference Manual: Analog Extensions to Verilog-HDL, version 1.0. Open Verilog International, 1996. Available from www.eda.org/verilogams.
10. K. Kundert, "Modeling and Simulation of Jitter in PLL Frequency Synthesizers," Available from www.desineers-guide.com.