0.622-8.0Gbps 150mW Serial IO Macrocell with Fully Flexible Preemphasis and Equalization

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 63-66

  Farjad Rad, Ramin ^a   Ng, Hiok Tiaq ^a   Lee, M J Edward ^a   Senthinathan, Ramesh ^a   Dally, William J ^b   Nguyen, Anhtuyet ^a   Rathi, Rohit ^a   Poulton, John ^a   Edmondson, John ^a   Tran, James ^a   Yazdanmehr, Hadi ^a  

^a Velio Communications Inc   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; INTERSYMBOL INTERFERENCE;

CLOCK MULTIPLICATION UNIT (CMU);

TRANSCEIVERS;

EID: 0141538244     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. F. Yang, et al., "A CMOS Low-Power Multiple 2.5-3.125-Gbps Serial Link Macrocell for High 10 Bandwidth Network ICs," IEEE J. Solid-State Circuits, pp.1813-1821, Dec. 2002
2. R. Farjadrad, et al., "A Low-Power Multiplying DLL for Low-jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips," IEEE J. Solid-State Circuits, pp.1804-1812, Dec. 2002
3. M.-J. E. Lee, et al., "A Second Order Semi-Digital Clock Recovery Circuit Based on Injection Locking," to appear in Dig. of Tech. papers, IEEE ISSCC, Feb. 2003
4. M.-J. E. Lee, et al., "A 90mW 4Gbps Equalized IO Circuit with Input Offset Cancellation," Dig. of Tech. papers, IEEE ISSCC, pp.252-253, Feb. 2000