Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 9, 2007, Pages 1999-2010

  Gondi, Srikanth ^b,c   Razavi, Behzad ^a,b  

^a IEEE

^b Engineering IV   (United States)

^c Kawasaki Microelectronics America Inc   (United States)

Author keywords

Adaptive equalization; Analog equalization; Broadband receivers; DFE; FFE; High speed links; Lossy channel; Reverse scaling

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC FILTERS; TOPOLOGY;

ADAPTIVE EQUALIZATION; ANALOG EQUALIZATION; BROADBAND RECEIVERS; HIGH-SPEED LINKS; LOSSY CHANNEL; REVERSE SCALING;

SIGNAL RECEIVERS;

EID: 34548234146     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.903076     Document Type: Conference Paper

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