Jitter amplification characterization of passive clock channels at 6.4 and 9.6 Gb/s

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2006, Pages 21-24

  Chaudhuri, Santanu ^a   Anderson, Warren ^a   Bryan, John ^a   McCall, James ^a   Dabral, Sanjay ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; ELECTRONICS PACKAGING;

ELECTRICAL PERFORMANCES; ELECTRONIC PACKAGING; JITTER AMPLIFICATION; SERIAL LINKS;

JITTER;

EID: 47949127880     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2006.321168     Document Type: Conference Paper

References (5)

1. PCIE Specification, http://www.pcisig.org.
2. Bryan K. Casper, Private Communication.
3. J.G. Proakis , Digital Communications, Fourth Edition, McGraw Hill, page 660.
4. G Balamurugan, N. Shanbhag, "Modeling and mitigation of jitter in high-speed source-synchronous I/O Links," International Conference on Computer Design, 2003.
5. Bryan K. Casper et al., "A 20 Gb/s Forwarded Clock Transceiver in 90 nm CMOS," International Symposium on Solid-State Circuits, 2006.