Modeling and mitigation of jitter in multi-Gbps source-synchronous I/O links

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 254-260

  Balamurugan, Ganesh ^a   Shanbhag, Naresh ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; COMMUNICATION CHANNELS (INFORMATION THEORY); FOURIER TRANSFORMS; FREQUENCY DOMAIN ANALYSIS; MATHEMATICAL MODELS; PERFORMANCE; SIGNAL RECEIVERS; TELECOMMUNICATION LINKS; TIME DOMAIN ANALYSIS; TIMING JITTER; TRANSFER FUNCTIONS; TRANSMITTERS;

DISCRETE TIME FOURIER TRANSFORM; JITTER TRANSFER FUNCTION; MAXIMUM ACHIEVABLE DATA RATES; SOURCE-SYNCHRONOUS I-O LINKS;

TIMING CIRCUITS;

EID: 0344119455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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