On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 3, 2003, Pages 336-344

  Zheng, Yu ^a   Shepard, Kenneth L ^a  

^a Department of Earth and Environmental Sciences   (United States)

Author keywords

Inductance modeling; Mixed signal test; Subsampling

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BUILT-IN SELF TEST; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; FREQUENCIES; INDUCTANCE; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SAMPLING; TIME DOMAIN ANALYSIS;

AUTOMATIC TEST PATTER GENERATION; DELAY LOCKED LOOPS; INDUCTANCE MODELLING; MIXED SIGNAL TEST; NONINVASIVE TIME DOMAIN MEASUREMENTS; ON-CHIP OSCILLOSCOPES; SUB SAMPLING;

MULTICHIP MODULES;

EID: 0041919508     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812313     Document Type: Article

References (21)

1. G. W. Roberts, "Improving the testability of mixed-signal integrated circuits," in Proc. Int. Custom Integrated Circuits Conf., 1997, pp. 214-221.
2. K. L. Shepard, D. Sitaram, and Y. Zheng, "Full-chip, three-dimensional, shapes-based RLC extraction," in Proc. Int. Conf. Computer-Aided Design, 2000, pp. 142-149.
3. W. R. Eisenstadt and Y. Eo, "S-parameter based IC interconnect transmission line characterization," IEEE Trans. Comp., Hydrids, and Manufact. Technol., vol. 15, no. 4, pp. 483-490, 1992.
4. B. Kleveland, C. H. Diaz, D. Vook, L. Madden, T. H. Lee, and S. S. Wong, "Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design," IEEE J. Solid-State Circuits, vol. 36, pp. 1480-1488, Oct. 2001.
5. A. Deutsch, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, L. M. Terman, Jr., R. P. Dunne, T. A. Gallo, and R. H. Dennard, "Modeling and characterization of long on-chip interconnections for high-performance microprocessors," IBM J. Res. Develop., vol. 39, no. 5, pp. 547-567, 1995.
6. K. Soumyanath, S. Borkar, C. Zhou, and B. A. Bloechel, "Accurate on-chip interconnect evaluation: a time-domain technique," IEEE J. Solid-State Circuits, vol. 34, pp. 623-631, May 1999.
7. P. Larsson and C. Svensson, "Measuring high-bandwidth signals in CMOS circuits," Electron. Lett., vol. 29, no. 20, pp. 1761-1762, Sept. 1993.
8. K. Lofstrom, "Early capture for boundary scan timing measurement," in Proc. IEEE Int. Test Conf., Oct. 1996, pp. 417-422.
9. M. A. Burns, "Understampling Digitizer With a Sampling Circuit Positioned on an Integrated Circuits," U. S. Patent 5 578 935, 1996.
10. A. Hajjar and G. W. Roberts, "A high speed and area efficient-on-chip analog waveform extractor," in Proc. IEEE Int. Test Conf., Oct. 1998, pp. 688-697.
11. R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. Horowitz, "Applications of on-chip samplers for test and measurement of integrated circuits," in Proc. Symp. VLSI Circuits Dig. Tech. Papers, 1998, pp. 138-139.
12. K. L. Shepard and Y. Zheng, "On-chip oscilloscopes for noninvasive time-domain measurement of waveforms," in Proc. Int. Conf. Comput. Design, 2001, pp. 221-226.
13. H. O. Johansson and C. Svensson, "Time resolution of NMOS sampling switches used on low-swing signals," IEEE J. Solid-State Circuits, vol. 33, pp. 237-245, Feb. 1998.
14. J. Christiansen, "An integrated high resolution CMOS timing generator based on an array of delay locked loops," IEEE J. Solid-State Circuits, vol. 31, pp. 952-957, July 1996.
15. C.-K. K. Yang and M. A. Horowitz, "A 0.8 μm CMOS 2.5 Gb/s over-sampling receiver and transmitter for serial links," IEEE J. Solid-State Circuits, vol. 31, pp. 2015-2023, Dec. 1996.
16. J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
17. J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
18. W. J. Dally and J. W. Poulton, Digital Systems Engineering. Cambridge, MA: Cambridge Univ. Press, 1998.
19. R. E. Suarez, P. R. Gray, and D. A. Hodges, "All-MOS charge redistribution analog-to-digital conversion techniques-part II," IEEE J. Solid-State Circuits, vol. SC-10, pp. 379-385, Dec. 1975.
20. B. Song, H. S. Lee, and M. Tompsett, "A 10-b 15-MHz CMOS recycling two-step A/D converter," IEEE J. Solid-State Circuits, vol. 25, pp. 1328-1338, Dec. 1990.
21. K. L. Shepard and Z. Tian, "Return-limited inductances: a practical approach to on-chip inductance extraction," IEEE Trans. Computer-Aided Design, vol. 19, pp. 425-436, Apr. 2000.