An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 54-57

  Casper, Bryan K ^a   Haycock, Matthew ^a   Mooney, Randy ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; CROSSTALK; INTERSYMBOL INTERFERENCE; JITTER; MATHEMATICAL MODELS; SIGNAL RECEIVERS; SPURIOUS SIGNAL NOISE;

CHIP TO CHIP SIGNALING SYSTEMS; POWER SUPPLY NOISE; RECEIVER JITTER;

SIGNAL THEORY;

EID: 0242695808     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. R. Nair, et al., "a 28.GB/s CMOS Non-Blocking Router for Terabits/s Connectivity between Multiple Processors and Peripheral I/O Nodes," ISSCC 2001 Digest of Technical Papers, Pap 14.7, February 2001.
4. M. Haycock, R. Mooney, "3.2GHz, 6.4Gb/s per wire signaling in 0.18μm CMOS," ISSCC 2001 Digest of Technical Papers, Pap 4.3, February 2001.
5. H. Wilson, M. Haycock, "A Six-Port 30-GB/s Nonblocking Router Component Using Point-to-Point Simultaneous Bidirectional Signaling for High-Bandwidth Interconnects," IEEE Journal of Solid-State Circuits, vol. 36, 12, pp. 1954-1963, December 2001.
6. M. Haycock et al., "A 2.5 Gb/s Bidirectional Signaling Technology," Hot Interconnects V Symposium Record, pp. 149-156, August 1997.
7. R. Mooney, C. Dike, S. Borkar, "A 900 Mb/s Bidirectional Signaling Scheme," IEEE Journal of Solid-State Circuits, vol. 30, issue 12, pp. 1538-1543, December 1995.