Clocking circuits for a 16Gb/s memory interface

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 435-438

  Wu, Ting ^a   Shi, Xudong ^a   Kaviani, Kambiz ^a   Lee, Haechang ^a   Chun, Jung Hoon ^a   Chin, T J ^a   Shen, Jie ^a   Perego, Rich ^a   Chang, Ken ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; JITTER; PHASE INTERFACES; PHASE LOCKED LOOPS;

65NM CMOS TECHNOLOGIES; DIGITALLY CONTROLLED; DUTY CYCLES; JITTER PERFORMANCES; MEMORY INTERFACES; PROTOTYPE CHIPS; WIDE FREQUENCY RANGES;

INTEGRATED CIRCUITS;

EID: 57849129407     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672114     Document Type: Conference Paper

References (7)

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3. K. Chang, et al., "A 0.44Gb/s CMOS Quad transceiver cell using on-chip regulated dual-loop PLLs," IEEE Symp. VLSI Circuits, pp.88-91, Jun. 2002.
4. E. Alon, et al., "Replica compensated linear regulators for supply regulated phase-locked loops," IEEE JSSC, vol. 41, pp. 413-424, Feb. 2006.
5. M. Meghelli, et al., "A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS," ISSCC Dig. Tech. Papers, pp.213-214, Feb. 2006.
6. J. Savoj and B. Razavi, "A CMOS interface circuit for detection of 1.2Gb/s RZ data," ISSCC Dig. Tech. Papers, pp.278-279, Feb. 1999.
7. C. Menolfi, et al., "A 16Gb/s source-series terminated transmitter in 65nm CMOS SOI," ISSCC Dig. Tech. Papers, pp.446-447, Feb. 2007.