A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1235-1247

  Lee, Haechang ^a   Chang, Kun Yung Ken ^a   Chun, Jung Hoon ^a,b   Wu, Ting ^a   Frans, Yohan ^a   Leibowitz, Brian ^a   Nguyen, Nhat ^a   Chin, T J ^a   Kaviani, Kambiz ^a   Shen, Jie ^a   Shi, Xudong ^a   Beyene, Wendemagegnehu T ^a   Li, Simon ^a   Navid, Reza ^a,c   Aleksic, Marko ^a   Lee, Fred S ^e   Quan, Fredy ^a   Zerbe, Jared ^a   Perego, Rich ^a,d   Assaderaghi, Fariborz ^e  

^a RAMBUS INC   (United States)

^b Sungkyunkwan University   (South Korea)

^c True Circuits Inc   (United States)

^d SiTime Corporation   (United States)

^e NONE

Author keywords

CMOS memory integrated circuits; DRAM chips; Equalizers; High speed integrated circuits; Interconnections; Intersymbol interference; Jitter; Synchronization; Transceivers

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONTROLLERS; DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION; INTEGRATED CIRCUITS; INTERSYMBOL INTERFERENCE; JITTER; PHASE INTERFACES; SURFACE CHEMISTRY; TIME MEASUREMENT; TRANSCEIVERS;

ASYMMETRIC LINKS; BANDWIDTH LIMITATIONS; CMOS MEMORY INTEGRATED CIRCUITS; DATA DEPENDENTS; DRAM CHIPS; HIGH DATA RATES; HIGH-SPEED INTEGRATED CIRCUITS; INTERCONNECTIONS; MEMORY INTERFACES; NYQUIST; OFF CHIPS; PHASE ERROR CORRECTIONS; PHYSICAL INTERFACES; TIMING CALIBRATIONS; TIMING MARGINS; WRITE OPERATIONS;

EQUALIZERS;

EID: 63449125471     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2014199     Document Type: Conference Paper

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