A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 126-127

  Chang, Ken ^a   Lee, Haechang ^a   Chun, Jung Hoon ^a   Wu, Ting ^a   Chin, T J ^a   Kaviani, Kambiz ^a   Shen, Jie ^a   Shi, Xudong ^a   Beyene, Wendem ^a   Frans, Yohan ^a   Leibowitz, Brian ^a   Nguyen, Nhat ^a   Quan, Fredy ^a   Zerbe, Jared ^a   Perego, Rich ^a   Assaderaghi, Fari ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY;

65NM CMOS; CONTROLLER INTERFACES; EQUALIZATION CIRCUITS; MEMORY COST; MEMORY INTERFACE; OPERATING CONDITION;

VLSI CIRCUITS;

EID: 51949114936     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585978     Document Type: Conference Paper

References (6)

1. K. Chang, et al., "A 2Gb/s/pin CMOS Asymmetric Serial Link," IEEE VLSI Circuit Symposium, 1998.
2. K. Chang, et al., "Clocking and Circuit Design for a Parallel I/O on a First Generation CELL Processor", IEEE, ISSCC 2005.
3. J. Zerbe, et al., "Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell", IEEE JSSC Dec 2003.
4. E. Sackinger, et al., "A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers," IEEE JSSC Dec 2000.
5. P. Favrat, et al., "A high-efficiency CMOS voltage doubler," IEEE JSSC, March 1998.
6. N. Nguyen, et al., "A 16-Gb/s Differential I/O Cell with 380fs RJ in an Emulated 40nm DRAM Process", submitted to VLSI Circuits 2008.