Design and analysis of a TB/sec memory system

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2008, Pages 21-24

  Beyene, Wendemagegnehu T ^a   Madden, Chris ^a   Kim, Namhoon ^a   Lee, Hae Chang ^a   Perego, Rich ^a   Seeker, Dave ^a   Yuan, Chuck ^a   Vaidyanath, Arun ^a   Chang, Ken ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AND MODELS; BIT ERRORS; DESIGN AND ANALYSES; INTERCONNECT TECHNOLOGIES; INTERFACE TECHNOLOGIES; MEMORY COSTS; MEMORY INTERFACES; MEMORY SYSTEMS; PROTOTYPE SYSTEMS; SYSTEM ANALYSIS; SYSTEM LEVELS; VOLTAGE MARGINS;

BIT ERROR RATE; DATA TRANSFER; DATA TRANSFER RATES; DESIGN; ELECTRONICS PACKAGING; TIME MEASUREMENT; TIMING CIRCUITS;

COST BENEFIT ANALYSIS;

EID: 58049107857     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2008.4675866     Document Type: Conference Paper

References (5)

1. K. Chang, et al, "A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface," IEEE VLSI Circuit Symposium, 2008.
2. N. Nguyen, et al, "A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process", IEEE VLSI Circuit Symposium, 2008.
3. T. Wu, et al, "Clocking circuits for a 16Gb/s memory interface," IEEE CICC, San Jose, CA, September 2008.
4. W. T. Beyene, et al, "System performance comparisons of coreless and standard packages for data rate beyond 20 Gbps," in the Proceedings of the 58th ECTC, Lake Buena, FL, May 27-30, 2008.
5. V. Stojanovic, Channel Limited High-Speed Links: Modeling, Analysis and Design, PhD Thesis, Stanford University, 2004.