Nanoelectronics: Nanotubes, nanowires, molecules, and novel concepts

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 55-61

  Wong, H S Philip ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC PROPERTIES; MECHANICAL PROPERTIES; NANOTUBES; OPTICAL PROPERTIES; QUANTUM THEORY; SELF ASSEMBLY;

MOLECULAR DEVICES; NANOELECTRONICS; NANOWIRES; SYSTEM ARCHITECTURES;

NANOTECHNOLOGY;

EID: 33751421252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546583     Document Type: Conference Paper

References (53)

1. th European Workshop on Ultimate Integration of Silicon, Leuven, Belgium, pp. 49-54, March 11-12, 2004
2. http://public.itrs.net
3. Ph. Avouris et al., Proc. IEEE, p. 1772, 2003
4. F.-L. Yang et al., "5 nm Gate Nanowire FinFET", Symp. VLSI Technology, p. 196-197, 2004
5. J. Appenzeller et al., IEDM Tech. Dig., p. 285, 2002
6. R. Martel, H.-S. P. Wong, K. Chan, and P. Avouris, "Carbon nanotube field effect transistors for logic applications," IEDM Tech. Dig., pp. 159-162, December 2001.
7. J. Guo, S. Datta, M. Lundstrom, M. Brink, P. McEuen, A. Javey, H. Dai, H. Kim, and P. McIntyre, "Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistors," IEDM Tech. Dig., pp. 711-714, December 2002.
8. H.-S P. Wong, J. Appenzeller, V. Derycke, R. Martel, S. Wind, and P. Avouris, "Carbon nanotube field effect transistors - fabrication, device physics, and circuit implications," IEEE International Solid-State Circuits Conference, vol. XLVI, pp. 370-371, February 2003.
9. J. Guo, A. Javey, H. Dai, and M. Lundstrom, "Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistors," IEDM Tech. Dig., pp. 703-706, December 2004.
10. R. Chau et al., "Emerging Silicon and Non-Silicon Nanoelectronic Devices: Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications," IEEE VLSI-TSA, (2005).
11. X. Wang, H.-S. P. Wong, P. Oldiges and R.J. Miller, "Electrostatic Analysis of Carbon Nanotube Arrays," 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Cambridge, MA, September 3-5, 2003.
12. A. Javey et al. IEDM Tech. Dig., p. 741, 2003
13. H.-S. P. Wong, "Beyond the conventional transistor," Solid State Electronics, vol. 49, pp. 755-72 (2005).
14. A. Javey, J. Guo, D. Farmer, Q. Wang, E. Yenilmez, R. Gordon, M. Lundstrom, H. Dai, "Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays," Nano Letters, vol. 4, No. 7, pp. 1319-1322 (2004).
15. A. Javey, R. Tu, D. Farmer, J. Guo, R. Gordon, H. Dai, "High performance n-type carbon nanotube field-effect transistors with chemically doped contacts," Nano Letters, vol. 5, No. 2, pp. 345-348 (2005).
16. S. Heinze, J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, and Ph. Avouris, "Carbon Nanotubes as Schottky Barrier Transistors," Phys. Rev. Lett. 89, 106801 (2002)
17. J. Guo, S. Datta, and M. Lundstrom, "A numerical study of scaling issues for Schottky-barrier carbon nanotube transistors," IEEE Trans. Electron Devices, Vol. 51, pp. 172-177, February 2004.
18. J. Appenzeller, M. Radosavljevi, J. Knoch, and Ph. Avouris, "Tunneling Versus Thermionic Emission in One-Dimensional Semiconductors," Phys. Rev. Lett. 92, 048301 (2004).
19. J. Chen, C. Klinke, A. Afzali, K. Chan, and P. Avouris, "Self-aligned carbon nanotube transistors with novel chemical doping," IEDM Tech. Dig., pp. 695-698, December 2004.
20. J. Appenzeller, J. Knoch, M. Radosavljevic, and Ph. Avouris, "Multimode Transport in Schottky-Barrier Carbon-Nanotube Field-Effect Transistors," Phys. Rev. Lett. 92, 226802 (2004).
21. S.-F. Huang et al., IEDM Tech. Dig., p. 237, 2001.
22. A. M. Morales, C. M. Leiber, "A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires," Science, vol. 279, p. 208 (1998).
23. Y. Huang et al., Science, 291 p. 630, 2001.
24. Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber, "Diameter-controlled synthesis of single-crystal silicon nanowires," Appl. Phys. Lett., vol. 78, p. 2214 (2001).
25. 2 gate dielectrics," Appl. Phys. Lett., vol. 83, p. 2432 (2003).
26. X. Duan, Y. Huang, Y. Cui, J. Wang, C. M. Lieber, "Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices," Nature, vol. 409, p. 66 (2001).
27. X. Duan, J. Wang, and C. M. Lieber, "Synthesis and optical properties of gallium arsenide nanowires," Appl. Phys. Lett. Vol. 76, p. 1116 (2000).
28. 2," Appl. Phys. Lett., vol. 75, p. 463 (1999).
29. G. Cheng, A. Kolmakov, Y. Zhang, M. Moskovits, R. Munden, M. A. Reed, G. Wang, D. Moses, and J.Zhang, "Current rectification in a single GaN nanowire with a well-defined p-n junction," Appl. Phys. Lett., vol. 83, p. 1578 (2003).
30. J.C. Johnson. H.-J. Choi, K.P. Knutsen. R.D. Schaller, P. Yang, R.J. Saykally, "Single gallium nitride nanowire lasers," Nature Materials, vol. 1, p. 106 (2002).
31. R. Kotlyar, B. Obradovic, P. Matagne, M. Stettler, and M. D. Giles, "Assessment of room-temperature phonon-limited mobility in gated silicon nanowires," Applied Physics Letters, Volume 84, Issue 25, pp. 5270-5272 (2004).
32. Y. Zheng, C. Rivas, R. Lake, K. Alam, T.B. Boykin, G. Klimeck, "Electronic properties of Silicon Nanowires," IEEE Trans. Electron Devices, pp. 1097-1103 (2005).
33. J. Tersoff, "Contact resistance of carbon nanotubes," Appl. Phys. Lett., vol. 74, No. 15, pp 2122-2124 (1999).
34. F. Léonard and J. Tersoff, "Novel Length Scales in Nanotube Devices," Phys. Rev. Lett., vol. 83, No. 24, pp. 5174-5177 (1999).
35. P.M. Solomon, S.E. Laux, "The Ballistic FET: Design, Capacitance and Speed Limit," IEDM Tech. Digest, pp. 95-98 (2001).
36. H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.-S. P. Wong, W. Haensch, "Electrical Characterization of Germanium p-Channel MOSFETs," IEEE Electron Device Letters, vol. 24, No. 4, pp. 242-244, April, 2003
37. M.C. McAlpine, R.S. Friedman, S. Jin, K.-H. Lin, W. U. Wang, and C.M. Lieber, "High-Performance Nanowire Electronics and Photonics on Glass and Plastic Substrates," Nano Letters, vol. 3, No. 11, pp. 1531-1535 (2003).
38. X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles & J. L. Goldman, "High-performance thin-film transistors using semiconductor nanowires and nanoribbons," Nature, vol. 425, p. 274 (2003).
39. A. Aviram and M. Ratner, Chem. Phys. Lett., p. 277, 1974.
40. B. Mantooth and P. S. Weiss, Proc. IEEE, p. 1785, 2003.
41. A. Salomon, D. Cahen, S. Lindsay, J. Tomfohr, V.B. Engelkes, C. D. Frisbie, "Comparison of electronic transport measurements on organic molecules," Advanced Materials, pp. 1881-1890 (2003).
42. H.-S. P. Wong, G. Ditlow, P.M. Solomon, X. Wang, "Performance Estimation and Benchmarking for Carbon Nanotube FETs and Nanodiode Arrays," Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, 802-803 (2003).
43. C. Kagan et al., Nano Letters, 3 (2), p. 119 (2003).
44. B. Doris et al., IEDM Tech. Dig., p. 267, 2002.
45. C. Joachim, J.K. Gimzewski and A. Aviram, "Electronics using hybrid-molecular and mono-molecular devices," Nature, 408, p. 541, 2000.
46. S. Gowda et al., IEDM Tech. Dig., paper 22.1, 2003.
47. K. Roth et al., J. Phys. Chem. B. 106, p. 8639 (2002).
48. A. DeHon, "Array-Based Architecture for FET-Based, Nanoscale Electronics," IEEE Trans. Nanotechnology, pp. 23-32 (2003).
49. C. Black and O. Bezencenet, "Nanometer-Scale Pattern Registration and Alignment by Directed Diblock Copolymer Self Assembly," IEEE Trans. Nanotechnology, p. 412, Sept. 2004
50. C. Mead and L. Conway, "Introduction to VLSI Systems," Addison-Wesley (1980).
51. J. Kouloheris and A. El Gamal, "PLA-based FPGA area vs. granularity," IEEE Custom Integrated Circuits Conference (CICC), pp. 4.3.1-4.3.4 (1991).
52. G. Ditlow and P. Solomon, unpublished, May 2003.
53. A. DeHon, S.C. Goldstein, P.J. Kuekes, and P. Lincoln, "Nonphotolithographic Nanoscale Memory Density Prospects," IEEE Trans. Nanotechnology, vol. 4, No. 2, pp. 215-228 (2005).