Nonphotolithographic nanoscale memory density prospects

IEEE Transactions on Nanotechnology

Volumn 4, Issue 2, 2005, Pages 215-228

  DeHon, André ^a   Goldstein, Seth Copen ^b   Kuekes, Philip J ^c   Lincoln, Patrick ^d  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b Carnegie Mellon University   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

^d SRI INTERNATIONAL   (United States)

Author keywords

Defect tolerance; Electronic nanotechnology; Memory density; Memory organization; Molecular electronics

Indexed keywords

CODES (SYMBOLS); DATA STORAGE EQUIPMENT; ERROR CORRECTION; ETCHING; LITHOGRAPHY; SELF ASSEMBLY; SEMICONDUCTOR JUNCTIONS;

DEFECT TOLERANCE; ELECTRONIC NANOTECHNOLOGY; MEMORY DENSITY; MEMORY ORGANIZATION; MOLECULAR ELECTRONICS;

NANOTECHNOLOGY;

EID: 15844425093     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.837849     Document Type: Article

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