Emerging silicon and non-silicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications

2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Volumn , Issue , 2005, Pages 13-16

  Chau, Robert ^a   Brask, Justin ^a   Datta, Suman ^a   Dewey, Gilbert ^a   Mark Doczy, Brian Doyle ^a   Kavalieros, Jack ^a   Jin, Ben ^a   Metz, Matthew ^a   Majumdar, Amlan ^a   Radosavljevic, Marko ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NANOELECTRONIC DEVICES; OFF-STATE LEAKAGE;

CARBON NANOTUBES; SEMICONDUCTOR QUANTUM WELLS; SILICON; TRANSISTORS;

NANOSTRUCTURED MATERIALS;

EID: 27144474479     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2005.1497062     Document Type: Conference Paper

References (24)

1. S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. McIntyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon", IEEE Electron Device Letters, vol. 25, pp. 191-193, 2004.
2. 2/TiN gate stack", IEDM Technical Digest, pp. 653-656, 2003.
3. 2 to high-κ", Extended Abstract of International Workshop on Gate Insulator, Tokyo, Japan, pp. 124-126, 2003.
4. th International Conference on Microelectronics and Interfaces, Santa Clara, CA, USA, pp. 3-5, 2004.
5. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-κ/metal-gate stack and its MOSFET characteristics", IEEE Electron Device Letters, vol. 25, pp. 408-409, 2004.
6. R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta, "Advanced depleted-substrate transistors: single-gate, double-gate and tri-Gate", Extended Abstracts of International Conference on Solid State Devices and Materials, Nagoya, Japan, pp. 68-69, 2002.
7. Y. Cui, X. Duan, J. Hu, and C. M. Lieber, "Doping and electrical transport in silicon nanowires", Journal of Physical Chemistry B, vol. 104, pp. 5213-5216, 2000.
8. L. J. Lauhon, M. S. Gudiksen, D. Wang, and C. M. Lieber, "Epitaxial core-shell and core-multishell nanowire heterostructures", Nature, vol. 420, pp. 57-61, 2002.
9. Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, "High performance silicon nanowire field effect transistors", Nano Letters, vol. 3, p. 149-152, 2003.
10. M. C. McAlpine, R. S. Friedman, S. Jin, K. Lin, W. U. Wang, and C. M. Lieber, "High-performance nanowire electronic and photonics on glass and plastic substrates", Nano Letters, vol. 3, pp. 1531-1535, 2003.
11. S. Jin, D. Whang, M. C. McAlpine, R. S. Friedman, Y. Wu, and C. M. Lieber, "Scalable interconnection and integration of nanowire devices without registration", Nano Letters, vol. 4, pp. 915-919, 2004.
12. A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Quo, P. McIntyre, P. McEuen, M. Lundstrom, and H. Dai, "High-κ dielectrics for advanced carbon nanotube transistors and logic gates", Nature Materials, vol. 1, pp. 241-246, 2002.
13. S. J. Wind, J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, "Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes", Applied Physics Letters, vol. 80, pp. 3817-3819, 2002.
14. S. Rosenblatt, Y. Yaish, J. Park, J. Gore, V. Sazonova, and P. L. McEuen, "High performance electrolyte gated carbon nanotube transistors", Nano Letters, vol. 2, pp. 869-872, 2002.
15. M. Radosavljevic, S. Heinze, J. Tersoff, and Ph. Avouris, "Drain voltage scaling in carbon nanotube transistors", Applied Physics Letters, vol. 83, pp. 2435-2437, 2003.
16. A. Javey, J. Guo, D. B. Farmer, Q. Wang, D. Wang, R. G. Gordon, M. Lundstrom, and H. Dai, "Carbon nanotube field-effect transistors with integrated ohmic contacts and high-κ gate dielectrics", Nano Letters, vol. 4, pp. 447-450, 2004.
17. A. Javey, J. Guo, D. B. Farmer, Q. Wang, E. Yenilmez, R. G. Gordon, M. Lundstrom, and H. Dai, "Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays", Nano Letters, vol. 4, pp. 1319-1322, 2004.
18. A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon, and H. Dai, "High performance n-type carbon nanotube field-effect transistors with chemically doped contacts", Nano Letters, vol. 5, pp. 345-348, 2005.
19. T. Ashley, A. B. Dean, C. T. Elliott, R. Jefferies, F. Khaleque, and T. J. Phillips, "High-speed low-power InSb transistors", IEDM Technical Digest, pp. 751-754, 1997.
20. th International Conference on Solid-State and Integrated Circuits Technology, Beijing, China, pp. 2253-2256, 2004.
21. th IEEE Conference on Nanotechnology, Munich, Germany, 2004.
22. R. Chau S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking nanotechnology for high-performance and low-power logic transistor applications", IEEE Transactions on Nanotechnology, vol. 4, March 2005.
23. R. Kotlyar, B. Obradovic, P. Matagne, M. Stettler, and M. D. Giles, "Assessment of room-temperature phonon-limited mobility in gated silicon nanowires", Applied Physics Letters, vol. 84, pp. 5270-5272, 2004.
24. M. S. Dresselhaus, G. Dresselhaus, and Ph. Avouris, Carbon nanotubes: Synthesis, Structure, Properties, and Applications, Berlin, Springer, 2001.