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2 and HBr was used to etch ∼660 nm trenches into the silicon wafer. The combination of gases was optimized to give 90° sidewalls, and the etch depth and angle were confirmed by SEM. The wafers were cleaned in an ozone-modified Huang clean and a 6 nm sacrificial oxide was grown and then removed by a modified Huang clean to reduce RIE damage and achieve smooth trench bottoms to ∼1 nm as confirmed by AFM measurements with a nanotube tip and SEM. A 30 nm oxide was grown to form the gate dielectric of the device structure.
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Efforts to etch vertical sidewalls in (100) n+ Si wafers were unsuccessful as the gas chemistries in n+ Si are not sufficiently selective and lateral etching occurs.
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0141435389
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2 hard mask, and the KOH solution etches into the Si wafer. The substrates were cleaned in water and dilute HCl. A 30 nm oxide was targeted, as used for the RIE trench above, to form the gate dielectric of the device structure. Since n+ silicon wafers oxidize more readily, the oxide thickness, using the same conditions as in (100) wafers, is ∼44 nm.
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Surfaces, whether metals or oxides that typically form the electrodes and dielectric layers of devices, become contaminated in the environment with inorganic and organic species. While quick exchange between vacuum and molecular solutions used for assembly may be suitable for device test structures fabricated from relatively nonreactive electrodes (such as Au, Pd, Pt) and oxide dielectrics, more reactive metals (such as Ni, Ti) and perhaps less common insulators will oxidize even upon short exposure to air. Exposure of surfaces to lithography resists and solvents limit the range of device fabrication schemes unless cleaning methods, such as solvent cleans or exposure to UV-ozone, are employed and qualified to yield reproducible and well-defined surfaces on which to build molecular devices.
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