An approach for improving the speed of content addressable memories

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Hyjazie, Jihad Mohammad ^a   Wang, Chunyan ^a  

^a Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; CAPACITANCE; DATA STORAGE EQUIPMENT; DATABASE SYSTEMS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); LOCAL AREA NETWORKS; SIGNAL PROCESSING;

POWER DISSIPATION;

ASSOCIATIVE STORAGE;

EID: 0038082072     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. Mundy, "High Density four-transistor MOS content addressable memory," U.S. Pat. 3 701 980, Oct. 1972.
2. J. P. Wade & C. G. Sodini, "Dynamic cross-coupled bitline content addressable memory cell for high density arrays," in IDEM Tech. Dig., Dec. 1985, pp. 284-287.
3. T. Yamagato, M. Mihara, T. Hamamoto, T. Kobayashi, and M. Yamada, "288-kbit fully parallel content addressable memory using stacked capacitor cell structure," in Proc CICC, May 1991, p. 10-3.
4. Valeries Lines, Abdullah Ahmed, Peter Ma, Stanley Ma, Rober McKenzie, Hong-Seok Kim, Cynthia Mar, Mosaid Technologies Incorporated, "66MHz 2.3M Ternary Dynamic Content Addressable Memory," in Record of the IEEE International Workshop on Memory Technology, Design and Testing p. 101-5, Aug. 2000.
5. Hisatada Mayatake, Masahiro Tanaka, Yotaro Mori, "A design for high-speed low power CMOS fully parallel content addressable memory macros," in IEEE 2001 J. Solid State Circuits, vol.36, pp.956-968, June 2001.
6. S. Jones, "Design selection and implementation of content addressable memory for a VLSI CMOS chip architecture," Proc. IEEE, vol. 135, pp.165-172, May 1988.