A design for high-speed low-power CMOS fully parallel content-addressable memory macros

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 6, 2001, Pages 956-968

  Miyatake, Hisatada ^a,b   Tanaka, Masahiro ^b   Mori, Yotaro ^b  

^a IEEE   (Japan)

^b IBM JAPAN LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONTENT ADDRESSABLE MEMORY MACROS; LOW POWER; MATCH LINE; SENSE AMPLIFIER;

AMPLIFIERS (ELECTRONIC); APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASSOCIATIVE STORAGE; BINARY CODES; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; NAND CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035369412     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.924858     Document Type: Article

References (19)

1. 2.6 Gbyte/s bandwidth cache/TLB macro for high-performance RISC processor
2. A 9-ns hit-delay 32-kbyte cache macro for high-speed RISC
3. A ternary content-addressable search engine
4. Associative processors and memories: A survey
5. A 20-kbit associative memory LSI for artificial intelligence machines
6. Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture
7. A 1.2-million transistor 33-MHz 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM
8. A 336-kbit content-addressable memory for highly parallel image processing
9. A fault-tolerant associative memory with high-speed operation
10. Real-time string search engine LSI for 800-Mbit/s LANs
11. Architectures for large-capacity CAMs
12. Fully parallel 25-MHz 2.5-Mb CAM
13. Content-addressable memory core cells: A survey
14. An 8-kbit content-addressable and reentrant memory
15. A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture
16. A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL
17. Fully parallel 30-MHz 2.5-Mb CAM