메뉴 건너뛰기




Volumn 36, Issue 6, 2001, Pages 956-968

A design for high-speed low-power CMOS fully parallel content-addressable memory macros

Author keywords

[No Author keywords available]

Indexed keywords

CONTENT ADDRESSABLE MEMORY MACROS; LOW POWER; MATCH LINE; SENSE AMPLIFIER;

EID: 0035369412     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.924858     Document Type: Article
Times cited : (115)

References (19)
  • 6
    • 0024011626 scopus 로고
    • Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture
    • May
    • (1988) Proc. IEEE , vol.135 , pp. 165-172
    • Jones, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.