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Volumn 36, Issue 6, 2001, Pages 956-968
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A design for high-speed low-power CMOS fully parallel content-addressable memory macros
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Author keywords
[No Author keywords available]
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Indexed keywords
CONTENT ADDRESSABLE MEMORY MACROS;
LOW POWER;
MATCH LINE;
SENSE AMPLIFIER;
AMPLIFIERS (ELECTRONIC);
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
ASSOCIATIVE STORAGE;
BINARY CODES;
CELLULAR ARRAYS;
CMOS INTEGRATED CIRCUITS;
ELECTRIC POWER SUPPLIES TO APPARATUS;
NAND CIRCUITS;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0035369412
PISSN: 00189200
EISSN: None
Source Type: Journal
DOI: 10.1109/4.924858 Document Type: Article |
Times cited : (115)
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References (19)
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