An adaptive serial-parallel CAM architecture for low-power cache blocks

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 136-141

  Efthymiou, Aristides ^a   Garside, Jim D ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

Asynchronous circuits; Cache design; CAM; Low energy; Low power; VLSI

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; DATA STRUCTURES; ELECTRIC POWER SUPPLIES TO APPARATUS; RANDOM ACCESS STORAGE; RESPONSE TIME (COMPUTER SYSTEMS); VLSI CIRCUITS;

ASYNCHRONOUS CIRCUITS; CACHE BLOCKS;

ASSOCIATIVE STORAGE;

EID: 0036949406     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146726     Document Type: Conference Paper

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