A novel low power CAM design

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 198-202

  Thirugnanam, Gandhi ^a,b   Vijaykrishnan, N ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; ASSOCIATIVE STORAGE; BUFFER STORAGE; DATABASE SYSTEMS; IMAGE PROCESSING;

CONTENT ADDRESSABLE MEMORY; TRANSLATION LOOK ASIDE BUFFER;

DATA STORAGE EQUIPMENT;

EID: 0034782018     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2001.954697     Document Type: Article

References (6)

1. Associative processors and memories: A survey
2. RAM versus CAM
3. Use of selective precharge for low-power content addressable memories
4. Reducing TLB power requirements
5. Fully parallel 30-MHz, 2.5 Mb CAM
6. Strong ARM SA110, a 160 MHz 32b 0.5w CMOS ARM processor