A current-saving match-line sensing scheme for content-addressable memories

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Arsovski, Igor ^a   Sheikholeslami, Ali ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHARGE TRANSFER; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENT CONTROL; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; INTERNET; MOSFET DEVICES; PACKET SWITCHING; ROUTERS; THRESHOLD VOLTAGE;

CURRENT RACE SENSING SCHEME; CURRENT SAVE SENSING; CURRENT SAVING MATCH LINE SENSING SCHEME; POWER REDUCTION; SEARCH LINES;

ASSOCIATIVE STORAGE;

EID: 0037630798     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. I. Y. L. Hsiao, D. H. Wang and C. W. Jen, "Power Modeling and Low-Power Design of Content Addressable Memories," IEEE ISCAS, Vol. 4, pp. 926-929, 2001.
2. I. Arsovski, T. Chandler, and A. Sheikholeslami, "A Ternary Content-Addressable Memory (TCAM) Based on 4T Static Storage and Including a Current-Race Sensing Scheme," to appear in the IEEE J. Solid State Circuits, Jan. 2003.
3. P. Lin and J. Kuo, "A 1-V 128-kb Four-Set-Associative CMOS Cache Memory Using Wordline-Oriented Tag Compare (WLOTC) Structure with Content-Addressable Memory (CAM) 10-Transistor Tag Cell," IEEE J. Solid State Circuits, Vol. 36, No. 4, pp. 666-676, Apr. 2001.
4. F. Shafai, K. J. Schultz, R. Gibson, et al., "Fully Parallel 30-MHz, 2.5-Mb CAM," IEEE J. Solid State Circuits, Vol. 33, No. 11, pp. 1690-1696, Nov. 1998.