A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 10, 2002, Pages 1307-1317

  Lin, Perng Fei ^a,b   Kuo, James B ^a,c  

^a IEEE   (Canada)

^b Goyatek Technology Inc   (Taiwan)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BITLINE-ORIENTED TAG-COMPARE; SHRUNK LOGIC SWING; SOFTWARE PACKAGE SPICE; TAG-SENSE AMPLIFIERS; WORDLINE-ORIENTED TAG-COMPARE;

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; TRANSISTORS; VLSI CIRCUITS;

CACHE MEMORY;

EID: 0036772124     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803023     Document Type: Article

References (8)

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