A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 4, 2005, Pages 853-860

  Hanzawa, Satoru ^a   Sakata, Takeshi ^a   Kajigaya, Kazuhiko ^b   Takemura, Riichiro ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

^b Elpida Memory Inc   (Japan)

Author keywords

Associative memory; Content addressable memory (CAM); DRAM; Hierarchical match line structure

Indexed keywords

BLOCK CODES; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POWER UTILIZATION; NETWORK PROTOCOLS; QUALITY OF SERVICE; SIGNAL ENCODING; SIGNAL PROCESSING;

ASSOCIATIVE MEMORY; CONTENT ADDRESSABLE MEMORY (CAM); HIERARCHICAL MATCH-LINE STRUCTURES; POWER CONSUMPTION;

ROUTERS;

EID: 18744362776     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.845554     Document Type: Conference Paper

References (11)

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