A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Choi, Sungdae ^a   Sohn, Kyomin ^a   Lee, Min Wuk ^a   Kim, Sunyoung ^a   Choi, Hye Mi ^a   Kim, Donghyun ^a   Cho, Uk Rae ^b   Byun, Hyun Geun ^b   Shin, Yun Seung ^b   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BANK ENABLE SIGNALS (BEN); COLUMN DECODING (CDE); PARTIAL MATCH BLOCKS (PM);

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DECODING; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; ROUTERS; STATIC RANDOM ACCESS STORAGE;

COMPUTER AIDED MANUFACTURING;

EID: 2442705704     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Farhad Shafai et al., "Fully Parallel 30MHz 2.5Mb CAM," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1690-1696, Nov. 1998.
2. Kenneth J. Schultz, P. Glenn Gulak, "Architectures for Large-Capacity CAMs," Integration, the VLSI Journal, pp. 151-171, 1995.
3. Igor Arsovski, Ali Sheikholeslami, "A Current-Saving Match-Line Sensing Scheme for Content-Addressable Memories," ISSCC Dig. Tech. Papers, pp. 304-305, Feb. 2003.
4. Uk-Rae Cho et al, "A 1.2V 1.5Gb/s 72Mb DDR3 SRAM," ISSCC Dig. Tech. Papers, pp. 300-301, Feb. 2003.