A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 4, 2001, Pages 712-716

  Liu, S C ^b   Wu, F A ^b   Kuo, James B ^a,c  

^a IEEE   (Canada)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

CMOS; Content addressable memory (CAM); Dynamic threshold (DTMOS); Low voltage; Partially depleted (PD) silicon on insulator (SOI); Tag cell; VLSI

Indexed keywords

CONTENT ADDRESSABLE MEMORY; DYNAMIC THRESHOLD; TAG CELL;

COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0035307445     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.913752     Document Type: Article

References (8)

1. An 8-kbit content-addressable and reentrant memory
2. Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI
3. Dynamic threshold pass-transistor logic for improved delay at low power supply voltages
4. A new SOI inverter using dynamic threshold for low-power applications
5. A 32-bit CMOS microprocessor with on-chip cache and TLB
6. Compact MOS/bipolar charge-control models of PD SOI CMOS devices for VLSI circuit simulation-SOI-technology SPICE