An AND-type match-line scheme for energy-efficient content addressable memories

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Wang, Jinn Shyan ^a   Li, Hung Yu ^a   Chen, Chia Cheng ^a   Yeh, Chingwei ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144447091     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. K. Pagiamtzis et al., "A Low-Power Content-Addressable Memory (CAM) Using Pipelined Hierarchical Search Scheme," IEEE J. Solid-State Circuits, vol. 39, pp. 1512-1519, Sept., 2004.
2. S. Choi et al., "A 0.7fJ/BitySearch, 2.2ns Search Time, Hybrid Type TCAM Architecture," ISSCC. Dig. Tech. Papers, pp. 498-507, Feb., 2004.
3. F. Shafai et al., "Fully parallel 30-MHz, 2.5-Mb CAM," IEEE J. Solid-State Circuits, vol. 33, pp. 1690-1696, Nov., 1998.
4. J.-R. Yuan et al., "New Domino Logic Precharged by Clock and Data," Electronics Letters, vol. 29, no. 25, pp. 2188-2189, Dec., 1993.
5. J.-S. Wang et al., "Analysis and Design of High-Speed and Low-Power CMOS PLAs," IEEE J. Solid-State Circuits, vol. 36, pp. 1250-1262, Aug., 2001.
6. O.T.-C. Chen et al., "A Power-Efficient Wide-Range Phase-Locked Loop," IEEE J. Solid-State Circuits, vol. 37, pp. 51-62, Jan., 2002.