Power modeling and low-power design of content addressable memories

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 926-929

  Hsiao, Ilion Yi Liang ^a   Wang, Ding Hao ^a   Jen, Chein Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BASE MODELS; CELL LAYOUT; CIRCUIT STRUCTURES; INPUT TRANSITION; LOOKUP ENGINES; LOW-POWER DESIGN; POWER PERFORMANCE; RANDOM INPUT;

TELECOMMUNICATION INDUSTRY;

ASSOCIATIVE STORAGE;

EID: 0038225842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922390     Document Type: Conference Paper

References (5)

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2. Prince B. Semiconductor Memories: A handbook of design, inamfacture, and application, 2nd ed. John Wiley & Sons, 1991.
3. Higuchi H., Tachibana S., Minnmi M and Nagano T. "A 2-ns, 5-mW. synchronous-powered static-circuit fully associative TLB." Dig, Syinp. VLSI Circuits, 1995.
4. Juan T., Lang T and Navarro J. J. "Reducing TLB power requirements." Proc. Iiitl. Syinp LOW Power Electronics and Design, 1997.
5. Hsiao I. Y.-L and Jen C.-W. "A new low-power content addressable memory design." Advanced IC design submission application report S39-895-56 to NSC CIC, Oct. 1000.