200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 387-390

  Kasai, Gen ^a   Takarabe, Yukihiro ^a   Furumi, Koji ^a   Yoneda, Masato ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; NUMERICAL METHODS;

BANK SELECTION SCHEME; CHARGE INJECTION MATCH DETECT CIRCUIT; DATA STORING METHOD; DISCHARGE CIRCUIT;

ASSOCIATIVE STORAGE;

EID: 0242443711     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. R. Panigraphy, S. Sharama, "Reducing TCAM power consumption and increasing throughput," Proc. 10th Symposium on High Performance Interconnects Hot Interconnects (HotI'02).
2. K. Schultz, F. Shafai, R. Gibson, A. Bluschke, D. Somppi, "Fully-Parallel 25MHz 2.5Mb CAM," Proc. IEEE ISSCC 1998.
3. I. Arsovski, A. Sheikholeslami, "A current-saving match-line sensing scheme for content-addressable memories," Proc. IEEE ISSCC 2003.
4. P. Lin, J. Kuo, "A 1-V 128-kb Four-Way Set-Associative CMOS Cache Memory Using Wordline-Oriented Tag-Compare (WLOTC) Structure with the Content-Addressable-Memory(CAM) 10-Transistor Tag Cell," IEEE J. Solid State Circuits, Vol.36, No. 4, pp. 666-676, Apr. 2001.